At the Cadence Academic Network contest for Best Master Thesis for academic chip designs, Vijayalakshmi Surendranath Shroff from the Chair for Circuit Design (Prof. Scheytt) has won the Cadence Academic Network Master Thesis Award 2022 for Analog Design with her master thesis on "Design of Low Phase Noise Amplifiers with 50 GHz bandwidth". She will present her work and receive the award at CadenceLive Europe which will be held on November 21-22 in Munich.
This contest was open for participants from EMEA (France, Germany, Finland, Sweden, Norway, Denmark, Belgium, the Netherlands, Luxemburg, Spain, Italy, Poland, Romania, Greece, and the United Kingdom) and the winner was selected by the program jury.
