Helmut Ngawa will present intermediate results of his master thesis with the topic "Konzeption und Implementierung einer HW/SW-Testumgebung für Funkschnittstellen einer modularen Entwicklungsplattform in der Automobilindustrie" on Thursday, February 14th. The Talk will start at 9am in Room P1.6.17.1. Everyone interested is invited to participate.

The Article "Divide and Compact — Stochastic Space Compaction for Faster-than-at-Speed Test" written by Alexander Sprenger and Sybille Hellebrand was accepted by the Journal of Circuits, Systems and Computers.

On Thursday, January 17th 2019, Jan Dennis Reimer will give the final talk about his project "Eine zeitbasierte SAT-Testmusterzeugung für kleine Verzögerungsfehler" (in German). The talk will start at 9:30am in our seminar room (P1.6.17.1). Everyone interested is cordially invited to join. Back to the list

The paper "A Hybrid Space Compactor for Varying X-Rates" from Mohammad Urf Maaz, Alexander Sprenger and Sybille Hellebrand is accepted for the 31.GI/GMM/ITG - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2019).

On Thursday, January 10th 2019, Mohammad Urf Maaz will give a talk about process variations and statistical timing analysis of digital circuits. The talk will start at 9:00am in our seminar room (P1.6.17.1). Everyone interested is cordially invited to join!

On Thursday, December 13th, Viktor Tran will give the inaugural lecture on his master's theseis on pareto-optimales SAT-ATPG. The lecture will take place at 9:30 in our seminar room (P1.6.17.1). All interested are cordially invited to!

On Thursday, November 11th, Mehak Aftab will give an interim lecture on her master's thesis X-ware Pattern Selection for Faster-than-at Speed Test. The lecture will take place at 9:30 in our seminar room (P1.6.17.1). All interested are cordially invited!

On October 11th, Dennis Reimer will give an intermediate talk about his project Zeitlich genaue SAT-basierte Testmustererzeugung. The talk will start at 9:30 am in our seminar room (P1.6.17.1). Everyone interested is cordially invited to join!

Matthias Kampmann and Sybille Hellebrand successfully submitted their contribution Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test to the IEEE "Workshop on RTL and High-Level Testing" (WRTLT). Matthias Kampmann will present the paper in October in China.

Am Donnerstag, den 13.09.2018 findet der 2. Klausurtermin der Veranstaltung "Grundlagen der Rechnerarchitektur" statt.

Manuel Boschmann will give his final talk on his bachelor thesis with the title: Implementierung und Analyse eines rekonfigurierbaren X-toleranten Signaturregisters on Wednesday, August 1st at 2pm in room P1.6.17.1. Everyone interested is invited to participate.

Matthias Kampmann and Sybille Hellebrand successfully submitted their article Built-in Test for Hidden Delay Faults, created in cooperation with Michael Kochte, Chang Liu, Eric Schneider and Hans-Joachim Wunderlich from the University of Stuttgart, to the IEEE journal "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems". The article will be published soon.

On Thursday, July 5th, Moritz Schniedermann will give his final presentation about his Masters Thesis SAT-basierte Testmustererzeugung für Verzögerungsfehler (in German). The talk will take place at 9:30am in our seminar room (P1.6.17.1). Everyone interested is cordially invited to join!

On Thursday, June 6th, the following talks will be given as part of our research seminar: - Mehak Aftab will give her introductory talk about her Masters Thesis X-Aware Pattern Selection for Faster-than-at-Speed Test - Viktor Tran and Jan Dennis Reimer will give their final presentation of their group project Fehleremulation für den Software-basierten Selbsttest - Eine experimentelle Evaluation für den Leon3-Prozessor The talks will start…

Alexander Sprenger and Sybille Hellabrand received the "Best Paper Award in the Area of Test" for their paper "Tuning Stochastic Space Compaction to Faster-than-At-Speed Test" during the "21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems" (DDECS) in Budapest.