Manuel Boschmann will give his final talk on his bachelor thesis with the title:
Implementierung und Analyse eines rekonfigurierbaren X-toleranten Signaturregisters
on Wednesday, August 1st at 2pm in room P1.6.17.1. Everyone interested is invited to participate.
Abstract:
The Faster-than-At-Speed Test (FAST) examines the circuit under test for small delay faults. These small delay faults can indicate early life failures, which is why it is important, especially in application areas that have high reliability requirements, that these faults are detected. One challenge is varying X-rates, which arise through the use of different observation times. Existing approaches to process X values are not capable of efficiently processing these varying X values. Therefore, the reconfigurable misr introduced in this thesis was implemented and analyzed. The approach is to use a reconfigurable misr and sort the scan chains in ascending order of X-rates. During FAST, e.g. after half of the observation times, the reconfigurable misr splits into several small misrs. Since the scan chains are sorted in ascending order, the scan chains with the lowest X-rates run into the first misr and the scan chain with the highest X-rates run into the last misr. If only the first misr is taken into account, and the remaining misrs are neglected, a high level of fault efficiency with a low intermediate signature storage size should be achieved.
Since the characteristic polynomial of the reconfigurable misr has to be adjusted when it splits, the effect of the characteristic polynomial on the fault efficiency and the intermediate signature storage size is examined. The simulation results have shown that the selection of the characteristic polynomial can increase the fault efficiency. In addition, it has been found that high fault efficiency also means that much intermediate signature storage is needed. In one example, the fault efficiency was increased by 6.7 % by changing the characteristic polynomial. However, the intermediate signature storage size has increased by 4.5 %. The misr size also strongly influences the observation variables. The smaller the misr, the higher the fault efficiency.
In the analysis of the reconfigurable misr, it has been found early on that many X-bits are associated with many D-bits. Therefore, the fault efficiency of the first misr into which the scan chains with low X-rates are running is too low, so the reconfigurable misr must be considered as a whole. The fault efficiency of a reconfigured misr, in which no single misr is neglected, is much higher than the fault efficiency of a non-reconfigurable misr of the same size. This can be exploited to increase the fault efficiency during FAST, reusing the misr of another test.