FAST – Re­li­ab­il­ity As­sess­ment us­ing „Faster-than-at-Speed Test“

Project sponsored by DFG, in cooperation with the University of Stuttgart

State-of-the-art nanoscale technologies allow for the integration of billions of transistors with feature sizes of 14 nm or below into a single chip. This enables innovative approaches and solutions in many application domains, but it also comes along with fundamental challenges. Early life failures are particularly critical, as they can cause product recalls associated with a loss of billions of dollars. A major cause of early life failures are  "weak" devices that operate correctly during manufacturing test, but cannot stand operational stress in the field. While other failure mechanisms, such as aging or external disturbances, to some extent, may be compensated by a robust design, potential early life failures must be detected by tests, and the respective systems have to be sorted out.

As they work properly in the beginning, weak structures must be identified by analyzing the non-functional circuit behavior with the help of appropriate observables. Besides power con­sumption, the circuit timing is one of the most important reliability indicators. In particular, small delay faults may indicate marginal hardware that can degrade further under stress. However, they can be “hidden” at nominal frequency and only be detected at higher frequencies (“faster-than-at-speed test” / FAST). Therefore, the test must be performed with increased clock frequency. However, this in turn creates new challenges, eg. cause by unstabilized circuit outputs ("unknowns"). The work in Paderborn concentrates on methods for the selection of optimal frequencies, test response compactioin in the presence of unknowns and built-in generation of FAST patterns.

Publications in peer reviewed conferences and journals

  • Logic Fault Diagnosis of Hidden Delay Defects
    2020 S. Holst, M. Kampmann, A. Sprenger, J. D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng
    Proceedings IEEE International Test Conference (ITC'20), Virtual Conference - Originally Washington, DC, USA, 3-5 November 2020, pp. 1-10
  • Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study
    2020 A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, S. Hellebrand
    Proceedings International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), Virtual Conference - Originally Frascati (Rome), Italy, 19-21 October 2020, pp. 1-6
  • Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
    2020 S. Sadeghi-Kohan, S. Hellebrand
    Proceedings IEEE VLSI Test Symposium (VTS'20), pp. 1-6
  • A Hybrid Space Compactor for Adaptive X-Handling
    2019 M. U. Maaz, A. Sprenger, S. Hellebrand
    Proceedings IEEE International Test Conference (ITC'19), Washington, DC, USA, 11-17 November 2019, pp. 1-8
  • Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test 
    2019, Sprenger Alexander, Sybille Hellebrand
    Journal of Circuits, Systems and Computers, World Scientific Pub Co Pte Lt, 2019
  • Built-in Test for Hidden Delay Faults
    2019 M. Kampmann, M. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), October 2019, Volume 38, Issue 10, pp. 1956-1968
  • Tuning Stochastic Space Compaction to Faster-than-At-Speed Test
    2018 A. Sprenger, S. Hellebrand
    Proceedings of 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2018), Budapest, Hungary, April 2018, 73-78
  • Design For Small Delay Test - A Simulation Study
    2018 M. Kampmann, S. Hellebrand
    Microelectronics Reliability, January 2018, Volume 80, pp 124-133
  • Design-for-FAST: Supporting X-tolerant Compaction during Faster-than-at-Speed Test
    2017 M. Kampmann, S. Hellebrand
    Proceedings 20th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), Dresden, Germany, April 2017, pp 39-45
  • X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test
    2016 S. Hellebrand, M. Kampmann
    Proceedings of 25th IEEE Asian Test Symposium (ATS'16), Hiroshima, Japan, November 2016, pp 1-6
  • Optimized Selection of Frequencies for Faster-than-at-Speed Test
    2015 M. Kampmann, M. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H. Wunderlich
    Proceedings Asian Test Symposium (ATS'15), Mumbai, India, November 2015, pp 109-114
  • FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects
    2014 S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Lui, H. Wunderlich
    Proceedings IEEE International Test Conference (ITC'14), Seattle, Washington USA, October 21-23, 2014

 

Further information: