On Thursday, July 5th, Moritz Schniedermann will give his final presentation about his Masters Thesis SAT-basierte Testmustererzeugung für Verzögerungsfehler (in German). The talk will take place at 9:30am in our seminar room (P1.6.17.1). Everyone interested is cordially invited to join!
Abstract
The test for transition delay faults in integrated circuits is crucial. In modern circuits, an increasing amount of small delay faults occur that do not lead to a failure during the test, but may be an indicator of a reliability threat. The Faster-than-at-Speed-Test (FAST) has become a feasible method to detect small delay faults by overclocking the circuit under test. As a result, a major challenge is the introduction of a high number of unknown values (X-values) into the test responses.
In the context of this master thesis, a SAT-based test pattern generation framework for transition delay faults is developed. SAT-based approaches transform the problem of test pattern generation into that of Boolean satisfiability. The flexibility and efficiency of this method shall be utilized to extend the transition fault model. Additional constraints guide the process of test pattern generation towards the generation of preferred patterns for FAST. A reduction in the switching activity of individual wires should reduce the introduction of X-values. Experimental results show that with this approach, the testability of small delay faults can be improved and the number of X-values can be reduced considerably.