Johannes Dorfschmidt will deliver the initial presentation of his bachelor thesis on Wednesday, January 31, 2024 at 15:00h. The title of the thesis is: "Machine Learning-based Detection and Diagnosis of Voids in Interconnections". The presentation will be given in english and take place in our seminar room P1.6.17.1. Everyone who is interested is welcome to attend the session.

We are pleased that our paper entitled "Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks" has been accepted at the workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'2024). The authors of the paper are Magdalina Ustimova, Somayeh Sadeghi-Kohan and Sybille Hellebrand. We are looking forward to presenting our research results at TuZ'2024. The workshop will take place in Darmstadt (Germany)…

We are pleased that our paper entitled "Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression" has been accepted at the workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'2024). The authors of the paper are Alisa Stiballe, Jan Dennis Reimer, Somayeh Sadeghi-Kohan and Sybille Hellebrand. We are looking forward to presenting our research results at TuZ'2024. The workshop will take place in Darmstadt…

Kai Arne Hannemann presents his master thesis on Wednesday, 25.10.2023 at 15:00 in our seminar room P1.6.17.1. The master thesis is titled: „Gate-All-Around Simulation with Neural Networks“. The presentation will be given in english. Everyone who is interested is welcome to attend the session. Abstract: Simulating gate-all-around (GAA) transistors using neural networks is a growing area of research that aims to overcome the limitations of…

Alisa Stiballe presents her bachelor thesis on Wednesday, 25.10.2023 at 14:00 in our seminar room P1.6.17.1. The bachelor thesis is titled: "GPU-based Logic Simulation of Crosstalk related Interconnect Delays". The presentation will be given in english. Everyone who is interested is welcome to attend the session. Abstract: The development of computer chips entails a sophisticated process requiring money, advanced knowledge, and time to…

The article "Robust Pattern Generation for Small Delay Faults under Process Variations" by Hanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi-Haghi, Hussam Amrouch, Sybille Hellebrand, and Hans-Joachim Wunderlich has been accepted at the IEEE International Test Conference 2023. Abstract: Small Delay Faults (SDFs) introduce additional delays smaller than the capture time and require timing-aware test pattern generation.…

The Article “Workload-Aware Periodic Interconnect BIST” written by Somayeh Sadeghi-Kohan, Sybille Hellebrand, and Hans-Joachim Wunderlich has been accepted by the IEEE Design & Test. Abstract: System-level interconnects provide the backbone for increasingly complex systems on a chip. Their vulnerability to electromigration and crosstalk can lead to serious reliability and safety issues during the system lifetime. This article presents an…

Justin Hendrichs presents his bachelor thesis on Wednesday, 02.08.2023 at 15:00 in our seminar room P1.6.17.1. The bachelor thesis is titled: "Zeitverhaltensanalyse mit SMT". The presentation will be given in German. Everyone who is interested is welcome to attend the session.

Alisa Stiballe presents her bachelor thesis on Wednesday, 26.07.2023 at 15:00 in our seminar room P1.6.17.1. The bachelor thesis is titled: "Gate-level Simulation of Crosstalk related Interconnect Delays on GPU". The presentation will be given in english. Everyone who is interested is welcome to attend the session.

On Wednesday, July 26th at 14:00 Magdalina Ustimova will give the final presentation on her bachelor thesis with the topic: "Simulation of interconnects using Artificial Neural Networks". The presentation will take place in the seminar room P1.6.17.1 and will be given in english. Everyone interested is invited to participate.

Felix Schönlau presents his bachelor thesis on Wednesday, 11.07.2023 at 15:00 in our seminar room P1.6.17.1. The bachelor thesis is titled: "Software-based Selftest for a RISC-V Prozessor". The presentation will be given in german. Everyone who is interested is welcome to attend the session.

Kai Arne Hannemann presents his state on the master thesis on Wednesday, 05.07.2023 at 15:00h in our seminar room P1.6.17.1. The master thesis is titled: "Neural Network based Gate-All Around Simulation". The presentation will be given in english. Everyone who is interested is welcome to attend the session.

The paper "Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication" was submitted by authors Somayeh Sadeghi-Kohan, Sybille Hellebrand und Hans-Joachim Wunderlich to the "53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'2023)" and accepted as a conference paper. The conference will be held in Porto (Portugal) from June 27-30, 2023.

Dr.-Ing. Matthias Kampmann presents his current research at Siemens EDA on Thursday 11.05.2023 at 14:00h in our seminar room P1.6.17.1. The presentation is titled: "Industrial Trends in DFT: IJTAG & SSN". The presentation will be given in german. Everyone who is interested is welcome to attend the session. Abstract In this talk, some of the recent DFT developments at Siemens EDA will be presented. The first part covers FastIJTAG, which is a…

On Wednesday April 26 at 3pm, Magdalina Ustimova will give an intermediate presentation on her bachelor thesis with the topic: "Simulation of Interconnects using Artificial Neural Networks". The presentation will be given in english and takes place in our seminar room P1.6.17.1. Everyone interested is invited to participate.