News

Fi­nal present­a­tion of Bach­el­or thes­is by Fady Youkeim

The final presentation of the bachelor thesis of Fady Youkeim will take place on Tuesday, December 10th at 15:00 in room P1.6.17.1. The title of his bachelor thesis is: "Efficient extension of the parameter space in GPU-based waveform simulation". The talk will be held in english. Everybody interested is invited to participate in the talk.

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Kick-off present­a­tion of Mas­ter thes­is by Kon­stantins Franck­evics

Konstantins Franckevics gives his inaugural talk of the master thesis on Tuesday, 22nd of October at 16.00h in Zoom. The title of the master thesis is: "Critical-area aware test pattern reordering". The talk will be held in english. Everybody interested is invited to participate in the talk.

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Pa­per ac­cep­ted for the "IEEE In­ter­na­tion­al Test Con­fer­ence" (ITC'24)

We are pleased to announce that our paper entitled "Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing" has been accepted for the "IEEE International Test Conference" (ITC'24) in San Diego, USA. This work is the result of a cooperation with the University of Stuttgart, the University of Paderborn and the Technical University of Munich (TUM). The authors involved are Hanieh Jafarzadeh,…

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Fi­nal present­a­tion of Bach­el­or thes­is by Jo­hannes Dorf­schmidt

Johannes Dorfschmidt presents his bachelor thesis on Tuesday, 30.07.2024 at 15.00h in our seminar room P1.6.17.1. The bachelor thesis is titled: "Machine Learning-based Detection and Diagnosis of Voids in Interconnections". The presentation will be given in English. Everyone interested is welcome to attend the session.

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Fi­nal present­a­tion of Bach­el­or thes­is by Justin Hendrichs

Justin Hendrichs presents his bachelor thesis on Wednesday, 19.06.2024 at 15:30h in our seminar room P1.6.17.1. The bachelor thesis is titled: "Zeitverhaltensanalyse mit SMT". The presentation will be given in German. Everyone who is interested is welcome to attend the session.

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Fi­nal present­a­tion of Bach­el­or thes­is by Fe­lix Schön­lau

Felix Schönlau presents his Bachelor thesis on Tuesday, 04.06.2024 at 15:00h in our seminar room P1.6.17.1. The bachelor thesis is titled: "Automatic Generation of Selftest programms for the RISC-V Processor". The presentation will be given in German. Everyone who is interested is welcome to attend the session.

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In­ter­me­di­ate present­a­tion of Bach­el­or thes­is by Justin Hendrichs

Justin Hendrichs presents his state on the bachelor thesis on Wednesday, 15.05.2024 at 11:00h in our seminar room P1.6.17.1. The bachelor thesis is titled: "Time analysis with SMT". The presentation will be given in German. Everyone who is interested is welcome to attend the session.

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Kick-off present­a­tion of Bach­el­or thes­is by Fady Youkeim

Fady Youkeim presents his bachelor thesis on Tuesday, 30.04.2024 at 10:00h in our seminar room P1.6.17.1. The bachelor thesis is titled: "Extending the transistor model in ThorSim to support multiple fins and process variations in waveform simulation". The presentation will be given in English. Everyone who is interested is welcome to attend the session.

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Ini­tial present­a­tion of Bach­el­or thes­is by Jo­hannes Dorf­schmidt

Johannes Dorfschmidt will deliver the initial presentation of his bachelor thesis on Wednesday, January 31, 2024 at 15:00h. The title of the thesis is: "Machine Learning-based Detection and Diagnosis of Voids in Interconnections". The presentation will be given in english and take place in our seminar room P1.6.17.1. Everyone who is interested is welcome to attend the session.

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Pa­per ac­cep­ted for the work­shop "Test­meth­oden und Zuver­lässigkeit von Schal­tun­gen und Syste­men" (TuZ'2024)

We are pleased that our paper entitled "Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks" has been accepted at the workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'2024). The authors of the paper are Magdalina Ustimova, Somayeh Sadeghi-Kohan and Sybille Hellebrand. We are looking forward to presenting our research results at TuZ'2024. The workshop will take place in Darmstadt (Germany)…

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Pa­per ac­cep­ted for the work­shop "Test­meth­oden und Zuver­lässigkeit von Schal­tun­gen und Syste­men" (TuZ'2024)

We are pleased that our paper entitled "Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression" has been accepted at the workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'2024). The authors of the paper are Alisa Stiballe, Jan Dennis Reimer, Somayeh Sadeghi-Kohan and Sybille Hellebrand. We are looking forward to presenting our research results at TuZ'2024. The workshop will take place in Darmstadt…

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Fi­nal present­a­tion of Mas­ter thes­is by Kai Arne Han­nemann

Kai Arne Hannemann presents his master thesis on Wednesday, 25.10.2023 at 15:00 in our seminar room P1.6.17.1. The master thesis is titled: „Gate-All-Around Simulation with Neural Networks“. The presentation will be given in english. Everyone who is interested is welcome to attend the session. Abstract: Simulating gate-all-around (GAA) transistors using neural networks is a growing area of research that aims to overcome the limitations of…

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Fi­nal present­a­tion of Bach­el­or thes­is by Al­isa Stiballe

Alisa Stiballe presents her bachelor thesis on Wednesday, 25.10.2023 at 14:00 in our seminar room P1.6.17.1. The bachelor thesis is titled: "GPU-based Logic Simulation of Crosstalk related Interconnect Delays". The presentation will be given in english. Everyone who is interested is welcome to attend the session. Abstract: The development of computer chips entails a sophisticated process requiring money, advanced knowledge, and time to…

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Art­icle "Ro­bust Pat­tern Gen­er­a­tion for Small Delay Faults un­der Pro­cess Vari­ations" ac­cep­ted at the IEEE In­ter­na­tion­al Test…

The article "Robust Pattern Generation for Small Delay Faults under Process Variations" by Hanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi-Haghi, Hussam Amrouch, Sybille Hellebrand, and Hans-Joachim Wunderlich has been accepted at the IEEE International Test Conference 2023. Abstract: Small Delay Faults (SDFs) introduce additional delays smaller than the capture time and require timing-aware test pattern generation.…

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Art­icle "Work­load-Aware Peri­od­ic In­ter­con­nect BIST" ac­cep­ted for IEEE Design & Test

The Article “Workload-Aware Periodic Interconnect BIST” written by Somayeh Sadeghi-Kohan, Sybille Hellebrand, and Hans-Joachim Wunderlich has been accepted by the IEEE Design & Test. Abstract: System-level interconnects provide the backbone for increasingly complex systems on a chip. Their vulnerability to electromigration and crosstalk can lead to serious reliability and safety issues during the system lifetime. This article presents an…

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