We are pleased to announce that our paper entitled "ThorSim: Throughput-Oriented Timing Simulation of FinFET Digital Circuits" has been accepted for the IEEE International Symposium of Electronics Design Automation (ISEDA'25) in Hong Kong, China. This work is the result of a co-operation with Paderborn University, Stuttgart University and Kyushu Institute of Technology. The authors involved are Jan Dennis Reimer, Stefan Holst, Somayeh Sadeghi-Kohan, Hans-Joachim Wunderlich and Sybille Hellebrand.
Abstract: Accurate timing analysis is crucial for design and verification. In addition, high throughput and scalability are required for simulation-based approaches, which often have to cope with large amounts of input data and a large number of large circuit instances. Existing approaches using a binary switch model offer an excellent compromise between accurate SPICE and high-performance gate-level simulation in planar CMOS. However, recent experiments have shown that the binary switch model is not accurate enough for FinFET technology. The new approach presented in this paper integrates an improved switch-level model into an efficient GPU-based simulation flow. High throughput is achieved by avoiding top-level event-driven control and enabling thread-parallel processing of independent components and input patterns. Experimental results confirm that the new approach accurately predicts the timing behaviour of digital circuits in modern CMOS technologies and scales well to multi-million transistor designs.