Matthias Kampmann und Sybille Hellebrand haben in Kooperation mit Michael Kochte, Chang Liu, Eric Schneider und Hans-Joachim Wunderlich von der Universität Stuttgart erfolgreich den Beitrag Built-in Test for Hidden Delay Faults beim IEEE-Journal "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems" eingereicht. Der Beitrag wird in Kürze veröffentlicht.
Abstract:
Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test.
This paper presents a fully autonomous built-in self-test (BIST) approach for FAST, which supports in-field testing by appropriate strategies for test generation and response compaction. In particular, the required test frequencies for hidden delay fault detection are selected, such that hardware overhead and test time are minimized. Furthermore, test response compaction handles the large number of unknowns (X-values) on long paths by storing intermediate MISR-signatures in a small on-chip memory for later analysis using X-canceling transformations. A comprehensive experimental study demonstrates the effectiveness of the presented approach. In particular, the impact of the considered fault size is studied in detail.
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