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Fachgebiet Datentechnik (DATE)
Prof. Dr. Sybille Hellebrand
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Stress-Aware Periodic Test of Interconnects

S. Sadeghi-Kohan, S. Hellebrand, H. Wunderlich, Journal of Electronic Testing (2022)

Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.


Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test

A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers (2019), 28(1), pp. 1-23

DOI


Built-in Test for Hidden Delay Faults

M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2019), 38(10), pp. 1956 - 1968

Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test.


Guest Editors' Introduction - Special Issue on Approximate Computing

S. Hellebrand, J. Henkel, A. Raghunathan, H. Wunderlich, IEEE Embedded Systems Letters (2018), 10(1), pp. 1-1

DOI


Design For Small Delay Test - A Simulation Study

M. Kampmann, S. Hellebrand, Microelectronics Reliability (2018), 80, pp. 124-133


Self-Adjusting Monitor for Measuring Aging Rate and Advancement

S. Sadeghi-Kohan, M. Kamal, Z. Navabi, IEEE Transactions on Emerging Topics in Computing (2017), 8(3), pp. 627-641

Time-variant age information of different parts of a system can be used for system-level performance improvement through high-level task scheduling, thus extending the life-time of the system. Progressive age information should provide the age state that the system is in, and the rate that it is being aged at. In this paper, we propose a structure that monitors certain paths of a circuit and detects its gradual age growth, and provides the aging rate and aging state of the circuit. The proposed monitors are placed on a selected set of nodes that represent a timing bottleneck of the system. These monitors sample expected data on these nodes, and compare them with the expected values. The timing of sampling changes as the circuit ages and its delay increases. The timing of sampling will provide a measure of aging advancement of a circuit. To assess the efficacy of the proposed method and compare it with other state-of-the-art aging monitors, we use them on selected nodes of the execution unit of different processors, as well as some circuits from ITC99 benchmarks. The results reveal that the precision of our proposed method is between 0.12 (ns) to 0.401 (ns). Its Area and power overhead are negligible and are about 2.13 and 0.69 percent respectively.


A High Performance SEU Tolerant Latch

Z. Huang, H. Liang, S. Hellebrand, Journal of Electronic Testing - Theory and Applications (JETTA) (2015), 31(4), pp. 349-359


SAT-Based ATPG beyond Stuck-at Fault Testing

S. Hellebrand, H. Wunderlich, DeGruyter Journal on Information Technology (it) (2014), 56(4), pp. 165-172


Adaptive Bayesian Diagnosis of Intermittent Faults

L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) (2014), 30(5), pp. 527-540


Variation-Aware Fault Modeling

F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich, SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer (2011), 54(4), pp. 1813-1826


Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance

S. Hellebrand, C. G. Zoellin, H. Wunderlich, S. Ludwig, T. Coym, B. Straube, Informacije MIDEM, Ljubljana (Invited Paper) (2007), 37(4 (124)), pp. 212-219


An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip

M. Ali, S. Hessler, M. Welzl, S. Hellebrand, International Journal on High Performance Systems Architecture (2007), 1(2), pp. 113-123


DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme

B. Becker, I. Polian, S. Hellebrand, B. Straube, H. Wunderlich, it - Information Technology (2006), 48(5), pp. 305-311


Efficient Online and Offline Testing of Embedded DRAMs

S. Hellebrand, H. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, IEEE Transactions on Computers (2002), 51(7), pp. 801-809

DOI


Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST

S. Hellebrand, H. Liang, H. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) (2002), 18(2), pp. 157-168


A Mixed-Mode BIST Scheme Based on Folding Compression

H. Liang, S. Hellebrand, H. Wunderlich, Journal on Computer Science and Technology (2002), 17(2), pp. 203-212


Deterministic BIST Scheme Based on Reseeding of Folding Counters

H. Liang, S. Hellebrand, H. Wunderlich, Journal of Computer Research and Development, (Jisuanji Yanjiu yu Fazhan) (2001), 38(8), pp. 931


A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters

S. Hellebrand, H. Liang, H. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) (2001), 17(3/4), pp. 341-349


Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications

S. Hellebrand, A. Hertwig, H. Wunderlich, IEEE Design and Test (1998), 15(4), pp. 36-41


Mixed-Mode BIST Using Embedded Processors

S. Hellebrand, H. Wunderlich, A. Hertwig, Journal of Electronic Testing Theory and Applications - JETTA (1998), 12(1/2), pp. 127-138


Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, IEEE Transactions on Computers (1995), 44(2), pp. 223-233

DOI


The Pseudoexhaustive Test of Sequential Circuits

H. Wunderlich, S. Hellebrand, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (1992), 11(1), pp. 26-33

DOI


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