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Fachgebiet Datentechnik (DATE)
Prof. Dr. Sybille Hellebrand
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Zeitschriften

  • Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test 
    2019, Sprenger Alexander, Sybille Hellebrand
    Journal of Circuits, Systems and Computers, World Scientific Pub Co Pte Lt, 2019
  • Built-in Test for Hidden Delay Faults
    2019 M. Kampmann, M. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Oktober 2019, Volume 38, Issue 10, pp. 1956-1968
  • Guest Editors' Introduction - Special Issue on Approximate Computing
    2018 S. Hellebrand, J. Henkel, A. Raghunathan, H.-J. Wunderlich
    IEEE Embedded Systems Letters, Vol. 10(1), März 2018, pp. 1-1
  • Design for Small Delay Test - A Simulation Study
    2018 M. Kampmann, S. Hellebrand
    Microelectronics Reliability 80, Januar 2018, pp 124-133
  • A High Performance SEU Tolerant Latch
    2015 Z. Huang, H. Liang, S. Hellebrand
    Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 31, No. 4, August 2015, pp. 349-359
  • Adaptive Bayesian Diagnosis of Intermittent Faults
    2014 L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H. Wunderlich
    Journal of Electronic Testing - Theory and Applications (JETTA), Oktober 2014, Volume 30, Issue 5, pp 527-540
  • SAT-Based ATPG beyond Stuck-at Fault Testing
    2014 S. Hellebrand, H. Wunderlich
    DeGruyter Journal on Information Technology (it), Juni 2014, Vol. 56 No. 4, pp 165-172
  • Signature rollback with extreme compaction - a technique for testing robust VLSI circuits with reduced hardware overhead
    2014 T. Indlekofer
    ANNALES Universitatis Scientiarum Budapestinensis de Rolando Eötvös Nominatae, Vol. 30, pp 161-180, 2013
  • Variation-Aware Fault Modeling
    2011 F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich
    SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer, Vol. 54, No. 4, pp. 1813-1826
  • New Self-Checking Booth Multipliers
    2008 M. Hunger, D. Marienfeld
    International Journal of Applied Mathematics and Computer Science Vol. 18, No. 3, 2008, DOI: 10.2478/v10006-008-0029-4
  • Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
    2007 S. Hellebrand, C. Zoellin, H. Wunderlich, S. Ludwig, T. Coym, B. Straube
    Informacije MIDEM, Vol. 37, No. 4(124), Ljubljana, Dezember 2007, pp. 212-219 (invited paper)
  • An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip
    2007 M. Ali, S. Hessler, M. Welzl, S. Hellebrand
    International Journal on High Performance Systems Architecture, Vol. 1, No. 2, 2007, pp. 113-123
  • DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme
    2006 B. Becker, I. Polian, S. Hellebrand, B. Straube, H. Wunderlich
    it - Information Technology, Vol. 48, No. 5, pp. 305-311, Oktober 2006
  • Efficient Online and Offline Testing of Embedded DRAMs
    2002 S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, V. Yarmolik
    IEEE Transactions on Computers, Vol. 51, No. 7, Juli 2002, pp. 801-809
  • Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
    2002 S. Hellebrand, H. Liang, H. Wunderlich
    Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 18, No. 2, April 2002, pp. 157-168
  • A mixed-mode BIST scheme based on folding compression
    2002 H. Liang, S. Hellebrand, H. Wunderlich
    Journal of Computer Science and Technology, März 2002, Vol. 17, issue 2, pp. 203-212
  • A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
    2001 S. Hellebrand, H. Liang, H. Wunderlich
    Journal of Electronic Testing - Theory and Applications, JETTA, Vol. 17, No. 3/4, Juni/August 2001, pp. 341-349
  • Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
    1998 S. Hellebrand, A. Hertwig, H. Wunderlich
    IEEE Design and Test, Vol. 15, No. 4, Oktober-Dezember 1998, pp. 36-41
  • Mixed-Mode BIST Using Embedded Processors
    1998 S. Hellebrand, H. Wunderlich, A. Hertwig
    Journal of Electronic Testing Theory and Applications - JETTA, Vol. 12, Nos. 1/2, Februar/April 1998, pp. 127-138
  • Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
    1995 S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois
    IEEE Transactions on Computers, Vol. 44, No. 2, Februar 1995, pp 223-233
  • The Pseudo-Exhaustive Test of Sequential Circuits
    1991 H. Wunderlich, S. Hellebrand
    IEEE Transactions on Computer-Aided Design of Intergated Circuits and Systems, Vol. 11, No. 1, Januar 1992, pp. 26-33

Zeitschriften RIS


Liste im Research Information System öffnen

The Pseudoexhaustive Test of Sequential Circuits

H. Wunderlich, S. Hellebrand, {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)} (1992), 11(1), pp. 26-33


Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, {IEEE Transactions on Computers} (1995), 44(2), pp. 223-233


Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications

S. Hellebrand, A. Hertwig, H. Wunderlich, {IEEE Design and Test} (1998), 15(4), pp. 36-41


Mixed-Mode BIST Using Embedded Processors

S. Hellebrand, H. Wunderlich, A. Hertwig, {Journal of Electronic Testing Theory and Applications - JETTA} (1998), 12(1/2), pp. 127-138


A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters

S. Hellebrand, H. Liang, H. Wunderlich, {Journal of Electronic Testing - Theory and Applications (JETTA)} (2001), 17(3/4), pp. 341-349


Deterministic BIST Scheme Based on Reseeding of Folding Counters

H. Liang, S. Hellebrand, H. Wunderlich, {Journal of Computer Research and Development, (Jisuanji Yanjiu yu Fazhan)} (2001), 38(8), pp. 931


A Mixed-Mode BIST Scheme Based on Folding Compression

H. Liang, S. Hellebrand, H. Wunderlich, {Journal on Computer Science and Technology} (2002), 17(2), pp. 203-212


Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST

S. Hellebrand, H. Liang, H. Wunderlich, {Journal of Electronic Testing - Theory and Applications (JETTA)} (2002), 18(2), pp. 157-168


Efficient Online and Offline Testing of Embedded DRAMs

S. Hellebrand, H. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, {IEEE Transactions on Computers} (2002), 51(7), pp. 801-809


DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme

B. Becker, I. Polian, S. Hellebrand, B. Straube, H. Wunderlich, {it -Information Technology} (2006), 48(5), pp. 305-311


An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip

M. Ali, S. Hessler, M. Welzl, S. Hellebrand, {International Journal on High Performance Systems Architecture} (2007), 1(2), pp. 113-123


Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance

S. Hellebrand, C. G. Zoellin, H. Wunderlich, S. Ludwig, T. Coym, B. Straube, {Informacije MIDEM, Ljubljana (Invited Paper)} (2007), 37(4 (124)), pp. 212-219


Variation-Aware Fault Modeling

F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich, {SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer} (2011), 54(4), pp. 1813-1826


SAT-Based ATPG beyond Stuck-at Fault Testing

S. Hellebrand, H. Wunderlich, DeGruyter Journal on Information Technology (it) (2014), 56(4), pp. 165-172


Adaptive Bayesian Diagnosis of Intermittent Faults

L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) (2014), 30(5), pp. 527-540


A High Performance SEU Tolerant Latch

Z. Huang, H. Liang, S. Hellebrand, Journal of Electronic Testing - Theory and Applications (JETTA) (2015), 31(4), pp. 349-359


Design For Small Delay Test - A Simulation Study

M. Kampmann, S. Hellebrand, Microelectronics Reliability (2018), 80, pp. 124-133


Guest Editors' Introduction - Special Issue on Approximate Computing

S. Hellebrand, J. Henkel, A. Raghunathan, H. Wunderlich, IEEE Embedded Systems Letters (2018), 10(1), pp. 1-1


Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test

A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers (2019), 28(1), pp. 1-23


Built-in Test for Hidden Delay Faults

M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2019), 38(10), pp. 1956 - 1968

Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test.


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