Elektrotechnik - Konferenzbeiträge (Universität Paderborn)

Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study

A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, 2020

Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects

S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS), IEEE, 2020

DOI

Logic Fault Diagnosis of Hidden Delay Defects

S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC'20), November 2020, 2020

A Hybrid Space Compactor for Adaptive X-Handling

M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, 2019, pp. 1-8

Abstract

The test for small delay faults is of major importance for predicting potential early life failures or wearout problems. Typically, a faster-than-at-speed test (FAST) with sev¬eral different frequencies is used to detect also hidden small delays, which can only be propagated over short paths. But then the outputs at the end of long paths may no longer reach their stable values at the nominal observation time and must be considered as unknown (X-values). Thus, test response compaction for FAST must be extremely flexible to cope with high X-rates, which also vary with the test frequencies. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals allowing for easy adaptation to varying conditions. As demonstrated in previous work, the pseudo-random control can be optimized for high fault efficiency or X-reduction, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on the observation that many faults are lost in the compaction of relatively few critical test patterns. For these critical patterns a deterministic compaction phase is added to the test, where the existing compactor structure is re-used, but controlled by specifically determined control vectors.

Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture

R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, Z. Navabi, in: Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018

Abstract

DOI

STT-RAM cells can be considered as an alternative or a hybrid addition to today's SRAM-based cache memories. This is mostly because of their scalability and low leakage power. Moreover, their data storing mechanism (storing the value as resistance) makes them very suitable and applicable for multivalue cache architectures. This feature results in system performance enhancement without any area overhead. On the other hand, the required two-step read/write procedure in multilevel cells results in a non-uniform time access and energy and power overhead on the system. In this paper, we propose a new architecture to dynamically swap data between soft (fast read access) and hard (slow read access) bits in ML cell. Moreover, by reconfiguring cache block size, the proposed architecture can switch between ML and SL modes at runtime. In other words, the swapping method places the hot part of each cache block into soft-bits and the less accessed part into the hard-bits. The SL/ML switching method benefits from the low latency and energy of SL mode and the high storing capacity of ML mode at the same time. Although experimental results show that our proposed method slightly increases the miss rate compared with the conventional ML caches, the performance and energy are improved by 4.9% and 6.5%, respectively. Also, the storage overhead of our method is about 1% that is negligible.

Near-Optimal Node Selection Procedure for Aging Monitor Placement

S. Sadeghi-Kohan, A. Vafaei, Z. Navabi, in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018

Abstract

DOI

Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. With the emergence of new issues like Electro-migration these problems are getting more crucial. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes that expose smaller overheads to the circuit, using correlation between nodes and the shareability amongst them. To select internal nodes, we first prune some nodes based on some attributes and thus provide a near-optimal solution that can effectively get a number of internal nodes and consider the effects of electro-migration as well. We have applied our proposed scheme to several processors and ITC benchmarks and have looked at its effectiveness for these circuits.

Tuning Stochastic Space Compaction to Faster-than-at-Speed Test

A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, 2018

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Extending Aging Monitors for Early Life and Wear-Out Failure Prevention

C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H. Wunderlich, in: 27th IEEE Asian Test Symposium (ATS'18), 2018

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Special Session on Early Life Failures

J. Deshmukh, W. Kunz, H. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI Test Symposium (VTS'17), IEEE, 2017

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Universal mitigation of NBTI-induced aging by design randomization

M. Jenihhin, A. Kamkin, Z. Navabi, S. Sadeghi-Kohan, in: 2016 IEEE East-West Design & Test Symposium (EWDTS), IEEE, 2017

Abstract

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In this paper we propose to think out of the box and discuss an approach for universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging untied from the limitations of its modelling. The cost-effective approach exploits a simple property of a randomized design, i.e., the equalized signal probability and switching activity at gate inputs. The techniques considered for structural design randomization involve both the hardware architecture and embedded software layers. Ultimately, the proposed approach aims at extending the reliable lifetime of nanoelectronic systems.

Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test

M. Kampmann, S. Hellebrand, in: 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS'17), IEEE, 2017

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X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test

M. Kampmann, S. Hellebrand, in: 25th IEEE Asian Test Symposium (ATS'16), IEEE, 2016, pp. 1-6

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Optimized Selection of Frequencies for Faster-Than-at-Speed Test

M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H. Wunderlich, in: 24th IEEE Asian Test Symposium (ATS'15), IEEE, 2015, pp. 109-114

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Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation

S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, Z. Navabi, in: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015

Abstract

DOI

Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of hardware aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes in combinational clouds between pipeline stages or combinational parts of a sequential circuit to place hardware monitors that can effectively provide aging information of various components of a modern digital system. In order to implement the node selection procedure, we propose an object-oriented model. Object-oriented model of a circuit along with a probabilistic and logical simulation engine that we have developed can effectively be used for implementation and also fast evaluation of the proposed node selection mechanism. The proposed object-oriented C+ + models can be integrated into a SystemC RTL model making it possible to perform mixed-level simulation, and integrated evaluation of a complete system. We have applied our proposed scheme to several processors including MIPS, ARM, ALPHA and MiniRISC and have looked at its effectiveness for these processors.

Online self adjusting progressive age monitoring of timing variations

S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, Z. Navabi, in: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015

Abstract

DOI

Transistor and interconnect wearout is accelerated with transistor scaling that results in timing variations. Progressive age measurement of a circuit can help a better prevention mechanism for reducing more aging. This requires age monitors that collect progressive age information of the circuit. This paper focuses on monitor structures for implementation of progressive age detection. The monitors are self-adjusting that they adjust themselves to detect progressive changes in the timing of a circuit. Furthermore, the monitors are designed for low hardware overhead, and certainty in reported timing changes.

FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects

S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, H. Wunderlich, in: IEEE International Test Conference (ITC'14), IEEE, 2014

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Analyzing and Quantifying Fault Tolerance Properties

S. Hellebrand, in: 14th IEEE Latin American Test Workshop - (LATW'13), IEEE, 2013

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Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test

A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, H. Wunderlich, in: 13th IEEE Latin American Test Workshop (LATW'12), IEEE, 2012, pp. 1-4

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Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test

A. Cook, S. Hellebrand, H. Wunderlich, in: 17th IEEE European Test Symposium (ETS'12), IEEE, 2012, pp. 1-6

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Diagnostic Test of Robust Circuits

A. Cook, S. Hellebrand, T. Indlekofer, H. Wunderlich, in: 20th IEEE Asian Test Symposium (ATS'11), IEEE, 2011, pp. 285-290

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Towards Variation-Aware Test Methods

I. Polian, B. Becker, S. Hellebrand, H. Wunderlich, P. Maxwell, in: 16th IEEE European Test Symposium Trondheim (ETS'11), IEEE, 2011

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Robuster Selbsttest mit Diagnose

A. Cook, S. Hellebrand, T. Indlekofer, H. Wunderlich, in: 5. GMM/GI/ITG Fachtagung "Zuverlässigkeit und Entwurf", 2011, pp. 48-53

Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits

B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich, in: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W'10), IEEE, 2010

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Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz

M. Hunger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", 2010, pp. 81-88

Variation-Aware Fault Modeling

F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich, in: 19th IEEE Asian Test Symposium (ATS'10), IEEE, 2010, pp. 87-93

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Efficient Test Response Compaction for Robust BIST Using Parity Sequences

T. Indlekofer, M. Schnittger, S. Hellebrand, in: 28th IEEE International Conference on Computer Design (ICCD'10), IEEE, 2010, pp. 480-485

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The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems

M. Hunger, S. Hellebrand, in: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10), IEEE, 2010, pp. 101-108

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Reusing NoC-Infrastructure for Test Data Compression

V. Froese, R. Ibers, S. Hellebrand, in: 28th IEEE VLSI Test Symposium (VTS'10), IEEE, 2010, pp. 227-231

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Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits

B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich, in: 4th Workshop on Dependable and Secure Nanocomputing (WDSN'10), (Invited Paper), 2010

Robuster Selbsttest mit extremer Kompaktierung

T. Indlekofer, M. Schnittger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", 2010, pp. 17-24

ATPG-Based Grading of Strong Fault-Secureness

M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 15th IEEE International On-Line Testing Symposium (IOLTS'09, IEEE, 2009

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Are Robust Circuits Really Robust?

S. Hellebrand, M. Hunger, in: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), (Invited Talk), IEEE, 2009, pp. 77

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Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung

M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 3. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", 2009

A Modular Memory BIST for Optimized Memory Repair

P. Oehler, A. Bosio, G. di Natale, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS'08), (Poster), IEEE, 2008

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Signature Rollback - A Technique for Testing Robust Circuits

U. Amgalan, C. Hachmann, S. Hellebrand, H. Wunderlich, in: 26th IEEE VLSI Test Symposium (VTS'08), IEEE, 2008, pp. 125-130

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Verification and Analysis of Self-Checking Properties through ATPG

M. Hunger, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS'08), IEEE, 2008

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Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG

M. Hunger, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", 2008

Modularer Selbsttest und optimierte Reparaturanalyse

P. Oehler, A. Bosio, G. Di Natale, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", 2008

A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction

S. Hellebrand, C. G. Zoellin, H. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'07), IEEE, 2007, pp. 50-58

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Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair

P. Oehler, S. Hellebrand, H. Wunderlich, in: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'07), IEEE, 2007, pp. 185-190

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An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy

P. Oehler, S. Hellebrand, H. Wunderlich, in: 12th IEEE European Test Symposium (ETS'07), IEEE, 2007, pp. 91-96

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Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance

S. Hellebrand, C. G. Zoellin, H. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), (Invited Paper), 2007

A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip

M. Ali, M. Welzl, S. Hessler, S. Hellebrand, in: 4th International Conference on Information Technology: New Generations (ITNG'07), 2007, pp. 1027-1032

Test und Zuverlässigkeit nanoelektronischer Systeme

B. Becker, I. Polian, S. Hellebrand, B. Straube, H. Wunderlich, in: 1. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", 2007

Considerations for Fault-Tolerant Networks on Chips

M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand, in: IEEE International Conference on Microelectronics (ICM'05), IEEE, 2005

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Low Power Embedded DRAMs with High Quality Error Correcting Capabilities

P. Oehler, S. Hellebrand, in: 10th IEEE European Test Symposium (ETS'05), IEEE, 2005, pp. 148-153

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A Dynamic Routing Mechanism for Network on Chip

M. Ali, M. Welzl, S. Hellebrand, in: 23rd IEEE NORCHIP Conference, IEEE, 2005, pp. 70-73

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Sensor Networks with More Features Using Less Hardware

M. Liu Jing, S. Ruehrup, C. Schindelhauer, K. Volbert, M. Dierkes, A. Bellgardt, R. Ibers, U. Hilleringmann, in: {GOR/NGB Conference Tilburg 2004}, 2004

Data Compression for Multiple Scan Chains Using Dictionaries with Corrections

A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: IEEE International Test Conference (ITC'04), IEEE, 2004, pp. 926-935

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A Hybrid Coding Strategy for Optimized Test Data Compression

A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: IEEE International Test Conference (ITC'03), IEEE, 2003, pp. 451-459

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Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST

H. Liang, S. Hellebrand, H. Wunderlich, in: IEEE International Test Conference (ITC'01), IEEE, 2001, pp. 894-902

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A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters

S. Hellebrand, H. Liang, H. Wunderlich, in: IEEE International Test Conference (ITC'00), IEEE, 2000, pp. 778-784

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Error Detecting Refreshment for Embedded DRAMs

S. Hellebrand, H. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, in: 17th IEEE VLSI Test Symposium (VTS'99), IEEE, 1999, pp. 384-390

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Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms

V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H. Wunderlich, in: Third European Dependable Computing Conference (EDCC-3), 1999

Symmetric Transparent BIST for RAMs

S. Hellebrand, H. Wunderlich, V. N. Yarmolik, in: Design Automation and Test in Europe (DATE'99), 1999, pp. 702-707

Fast Self-Recovering Controllers

A. Hertwig, S. Hellebrand, H. Wunderlich, in: 16th IEEE VLSI Test Symposium (VTS'98), IEEE, 1998, pp. 296-302

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Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs

S. Hellebrand, H. Wunderlich, V. N. Yarmolik, in: Design Automation and Test in Europe (DATE'98), 1998, pp. 173-179

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New Transparent RAM BIST Based on Self-Adjusting Output Data Compression

V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, H. Wunderlich, in: Design & Diagnostics of Electronic Circuits & Systems (DDECS'98), 1998, pp. 27-33

STARBIST: Scan Autocorrelated Random Pattern Generation

K. Tsai, S. Hellebrand, M. Marek-Sadowska, J. Rajski, in: 34th ACM/IEEE Design Automation Conference (DAC'97), IEEE, 1997

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Mixed-Mode BIST Using Embedded Processors

S. Hellebrand, H. Wunderlich, A. Hertwig, in: IEEE International Test Conference (ITC'96), IEEE, 1996, pp. 195-204

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Pattern Generation for a Deterministic BIST Scheme

S. Hellebrand, B. Reeb, S. Tarnick, H. Wunderlich, in: ACM/IEEE International Conference on Computer Aided Design (ICCAD'95), IEEE, 1995, pp. 88-94

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An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures

S. Hellebrand, H. Wunderlich, in: ACM/IEEE International Conference on Computer-Aided Design (ICCAD'94), IEEE, 1994, pp. 110-116

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Synthese schneller selbsttestbarer Steuerwerke

S. Hellebrand, H. Wunderlich, in: Tagungsband der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1994, pp. 3-11

Synthesis of Self-Testable Controllers

S. Hellebrand, H. Wunderlich, in: European Design and Test Conference (EDAC/ETC/EUROASIC), 1994, pp. 580-585

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An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers

S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick, in: ACM/IEEE International Conference on Computer Aided Design (ICCAD'93), IEEE, 1993

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Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, in: IEEE International Test Conference (ITC'92), IEEE, 1992, pp. 120-129

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Tools and Devices Supporting the Pseudo-Exhaustive Test

S. Hellebrand, H. Wunderlich, in: European Design Automation Conference (EDAC'90), IEEE, 1990, pp. 13-17

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Generating Pseudo-Exhaustive Vectors for External Testing

S. Hellebrand, H. Wunderlich, O. F. Haberl, in: IEEE International Test Conference (ITC'90), IEEE, 1990, pp. 670-679

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The Pseudo-Exhaustive Test of Sequential Circuits

H. Wunderlich, S. Hellebrand, in: IEEE International Test Conference (ITC'89), IEEE, 1989, pp. 19-27

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Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits

H. Wunderlich, S. Hellebrand, in: 18th International Symposium on Fault-Tolerant Computing, FTCS-18, 1988, pp. 36-45

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Integrated Tools for Automatic Design for Testability

D. Schmid, H. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, A. Kunzmann, in: Tool Integration and Design Environments, F.J. Rammig (Editor), Amsterdam: Elsevier Science Publishers B.V.(North Holland), IFIP, 1988, pp. 233-258

Automatisierung des Entwurfs vollständig testbarer Schaltungen

S. Hellebrand, H. Wunderlich, in: GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, Springer Verlag, 1988, pp. 145-159

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