Konferenzbeiträge
Robust Pattern Generation for Small Delay Faults under Process Variations
H. Jafarzadeh, F. Klemme, J.D. Reimer, Z.P. Najafi Haghi, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: To Appear: IEEE International Test Conference (ITC’23), October 2023, Anaheim, CA, USA, 2023.
Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, in: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023.
Optimizing the Streaming of Sensor Data with Approximate Communication
S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, in: To Appear: IEEE Asian Test Symposium (ATS’23), October 2023, Beijing, China, 2023.
Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study
A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.
Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS), IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.
Logic Fault Diagnosis of Hidden Delay Defects
S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual Conference - Originally Washington, DC, USA, 2020.
A Hybrid Space Compactor for Adaptive X-Handling
M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.
Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture
R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, Z. Navabi, in: Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018.
Tuning Stochastic Space Compaction to Faster-than-at-Speed Test
A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Budapest, Hungary, 2018.
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention
C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in: 27th IEEE Asian Test Symposium (ATS’18), 2018.
Near-Optimal Node Selection Procedure for Aging Monitor Placement
S. Sadeghi-Kohan, A. Vafaei, Z. Navabi, in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018.
Special Session on Early Life Failures
J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI Test Symposium (VTS’17), IEEE, Caesars Palace, Las Vegas, Nevada, USA, 2017.
Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test
M. Kampmann, S. Hellebrand, in: 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17), IEEE, 2017.
Universal mitigation of NBTI-induced aging by design randomization
M. Jenihhin, A. Kamkin, Z. Navabi, S. Sadeghi-Kohan, in: 2016 IEEE East-West Design & Test Symposium (EWDTS), IEEE, 2017.
X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test
M. Kampmann, S. Hellebrand, in: 25th IEEE Asian Test Symposium (ATS’16), IEEE, Hiroshima, Japan, 2016, pp. 1–6.
Optimized Selection of Frequencies for Faster-Than-at-Speed Test
M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, in: 24th IEEE Asian Test Symposium (ATS’15), IEEE, Mumbai, India, 2015, pp. 109–114.
Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation
S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, Z. Navabi, in: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.
Online self adjusting progressive age monitoring of timing variations
S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, Z. Navabi, in: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.
FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects
S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’14), IEEE, Seattle, Washington, USA, 2014.
An off-line MDSI interconnect BIST incorporated in BS 1149.1
M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, Z. Navabi, in: 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014.
Improving polynomial datapath debugging with HEDs
S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, Z. Navabi, in: 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014.
Analyzing and Quantifying Fault Tolerance Properties
S. Hellebrand, in: 14th IEEE Latin American Test Workshop - (LATW’13), IEEE, Cordoba, Argentina, 2013.
BS 1149.1 extensions for an online interconnect fault detection and recovery
S. Sadeghi-Kohan, M. Namaki-Shoushtari, F. Javaheri, Z. Navabi, in: 2012 IEEE International Test Conference, IEEE, 2013.
A new structure for interconnect offline testing
S. Sadeghi-Kohan, S. Keshavarz, F. Zokaee, F. Farahmandi, Z. Navabi, in: East-West Design & Test Symposium (EWDTS 2013), IEEE, 2013.
Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test
A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, H.-J. Wunderlich, in: 13th IEEE Latin American Test Workshop (LATW’12), IEEE, Quito, Ecuador, 2012, pp. 1–4.
Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test
A. Cook, S. Hellebrand, H.-J. Wunderlich, in: 17th IEEE European Test Symposium (ETS’12), IEEE, Annecy, France, 2012, pp. 1–6.
Diagnostic Test of Robust Circuits
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 20th IEEE Asian Test Symposium (ATS’11), IEEE, New Delhi, India, 2011, pp. 285–290.
Towards Variation-Aware Test Methods
I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, P. Maxwell, in: 16th IEEE European Test Symposium Trondheim (ETS’11), IEEE, Trondheim, Norway, 2011.
Robuster Selbsttest mit Diagnose
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf,” Hamburg, Germany, 2011, pp. 48–53.
Virtual tester development using HDL/PLI
A. Kamran, N. Nemati, S. Sadeghi-Kohan, Z. Navabi, in: 2010 East-West Design & Test Symposium (EWDTS), IEEE, 2011.
Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), IEEE, Chicago, IL, USA, 2010.
Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz
M. Hunger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 81–88.
Variation-Aware Fault Modeling
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 19th IEEE Asian Test Symposium (ATS’10), IEEE, Shanghai, China, 2010, pp. 87–93.
Efficient Test Response Compaction for Robust BIST Using Parity Sequences
T. Indlekofer, M. Schnittger, S. Hellebrand, in: 28th IEEE International Conference on Computer Design (ICCD’10), IEEE, Amsterdam, The Netherlands, 2010, pp. 480–485.
The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems
M. Hunger, S. Hellebrand, in: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, Kyoto, Japan, 2010, pp. 101–108.
Reusing NoC-Infrastructure for Test Data Compression
V. Froese, R. Ibers, S. Hellebrand, in: 28th IEEE VLSI Test Symposium (VTS’10), IEEE, Santa Cruz, CA, USA, 2010, pp. 227–231.
Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), Chicago, IL, USA, 2010.
Robuster Selbsttest mit extremer Kompaktierung
T. Indlekofer, M. Schnittger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 17–24.
ATPG-Based Grading of Strong Fault-Secureness
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, Sesimbra-Lisbon, Portugal, 2009.
Are Robust Circuits Really Robust?
S. Hellebrand, M. Hunger, in: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, Chicago, IL, USA, 2009, p. 77.
Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Stuttgart, Germany, 2009.
A Modular Memory BIST for Optimized Memory Repair
P. Oehler, A. Bosio, G. di Natale, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster), IEEE, Rhodos, Greece, 2008.
Signature Rollback - A Technique for Testing Robust Circuits
U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, in: 26th IEEE VLSI Test Symposium (VTS’08), IEEE, San Diego, CA, USA, 2008, pp. 125–130.
Verification and Analysis of Self-Checking Properties through ATPG
M. Hunger, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS’08), IEEE, Rhodos, Greece, 2008.
Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG
M. Hunger, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Ingolstadt, Germany, 2008.
Modularer Selbsttest und optimierte Reparaturanalyse
P. Oehler, A. Bosio, G. Di Natale, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Ingolstadt, Germany, 2008.
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), IEEE, Rome, Italy, 2007, pp. 50–58.
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, Krakow, Poland, 2007, pp. 185–190.
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 12th IEEE European Test Symposium (ETS’07), IEEE, Freiburg, Germany, 2007, pp. 91–96.
Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper), Bled, Slovenia, 2007.
A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip
M. Ali, M. Welzl, S. Hessler, S. Hellebrand, in: 4th International Conference on Information Technology: New Generations (ITNG’07), Las Vegas, Nevada, USA, 2007, pp. 1027–1032.
Test und Zuverlässigkeit nanoelektronischer Systeme
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, in: 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Munich, Germany, 2007.
Considerations for Fault-Tolerant Networks on Chips
M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand, in: IEEE International Conference on Microelectronics (ICM’05), IEEE, Islamabad, Pakistan, 2005.
Low Power Embedded DRAMs with High Quality Error Correcting Capabilities
P. Oehler, S. Hellebrand, in: 10th IEEE European Test Symposium (ETS’05), IEEE, Tallinn, Estonia, 2005, pp. 148–153.
A Dynamic Routing Mechanism for Network on Chip
M. Ali, M. Welzl, S. Hellebrand, in: 23rd IEEE NORCHIP Conference, IEEE, Oulu, Finland, 2005, pp. 70–73.
Sensor Networks with More Features Using Less Hardware
M. Liu Jing, S. Ruehrup, C. Schindelhauer, K. Volbert, M. Dierkes, A. Bellgardt, R. Ibers, U. Hilleringmann, in: {GOR/NGB Conference Tilburg 2004}, Tilburg, Netherlands, 2004.
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: IEEE International Test Conference (ITC’04), IEEE, Charlotte, NC, USA, 2004, pp. 926–935.
A Hybrid Coding Strategy for Optimized Test Data Compression
A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: IEEE International Test Conference (ITC’03), IEEE, Charlotte, NC, USA, 2003, pp. 451–459.
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’01), IEEE, Baltimore, MD, USA, 2001, pp. 894–902.
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’00), IEEE, Atlantic City, NJ, USA, 2000, pp. 778–784.
Error Detecting Refreshment for Embedded DRAMs
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, in: 17th IEEE VLSI Test Symposium (VTS’99), IEEE, Dana Point, CA, USA, 1999, pp. 384–390.
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms
V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H.-J. Wunderlich, in: Third European Dependable Computing Conference (EDCC-3), Prague, Czech Republic, 1999.
Symmetric Transparent BIST for RAMs
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: Design Automation and Test in Europe (DATE’99), Munich, Germany, 1999, pp. 702–707.
Fast Self-Recovering Controllers
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, in: 16th IEEE VLSI Test Symposium (VTS’98), IEEE, Monterey, CA, USA, 1998, pp. 296–302.
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: Design Automation and Test in Europe (DATE’98), Paris, France, 1998, pp. 173–179.
New Transparent RAM BIST Based on Self-Adjusting Output Data Compression
V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, H.-J. Wunderlich, in: Design & Diagnostics of Electronic Circuits & Systems (DDECS’98), Szczyrk, Poland, 1998, pp. 27–33.
STARBIST: Scan Autocorrelated Random Pattern Generation
K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, J. Rajski, in: 34th ACM/IEEE Design Automation Conference (DAC’97), IEEE, Anaheim, CA, USA, 1997.
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: IEEE International Test Conference (ITC’96), IEEE, Washington, DC, USA, 1996, pp. 195–204.
Pattern Generation for a Deterministic BIST Scheme
S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, in: ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), IEEE, San Jose, CA, USA, 1995, pp. 88–94.
An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures
S. Hellebrand, H.-J. Wunderlich, in: ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), IEEE, San Jose, CA, USA, 1994, pp. 110–116.
Synthese schneller selbsttestbarer Steuerwerke
S. Hellebrand, H.-J. Wunderlich, in: Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, Oberwiesenthal, Informatik Xpress 4, TU Chemnitz Zwickau, Germany, 1994, pp. 3–11.
Synthesis of Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, in: European Design and Test Conference (EDAC/ETC/EUROASIC), Paris, France, 1994, pp. 580–585.
An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers
S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick, in: ACM/IEEE International Conference on Computer Aided Design (ICCAD’93), IEEE, 1993.
Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, in: IEEE International Test Conference (ITC’92), IEEE, Baltimore, MD, USA, 1992, pp. 120–129.
Tools and Devices Supporting the Pseudo-Exhaustive Test
S. Hellebrand, H.-J. Wunderlich, in: European Design Automation Conference (EDAC’90), IEEE, Glasgow, UK, 1990, pp. 13–17.
Generating Pseudo-Exhaustive Vectors for External Testing
S. Hellebrand, H.-J. Wunderlich, O. F. Haberl, in: IEEE International Test Conference (ITC’90), IEEE, Washington, DC, USA, 1990, pp. 670–679.
The Pseudo-Exhaustive Test of Sequential Circuits
H.-J. Wunderlich, S. Hellebrand, in: IEEE International Test Conference (ITC’89), IEEE, Washington, DC, USA, 1989, pp. 19–27.
Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits
H.-J. Wunderlich, S. Hellebrand, in: 18th International Symposium on Fault-Tolerant Computing, FTCS-18, Tokyo, Japan, 1988, pp. 36–45.
Integrated Tools for Automatic Design for Testability
D. Schmid, H.-J. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, A. Kunzmann, in: Tool Integration and Design Environments, F.J. Rammig (Editor), Amsterdam: Elsevier Science Publishers B.V.(North Holland), IFIP, Amsterdam, The Netherlands, 1988, pp. 233–258.
Automatisierung des Entwurfs vollständig testbarer Schaltungen
Alle Publikationen anzeigen
S. Hellebrand, H.-J. Wunderlich, in: GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, Springer Verlag, Hamburg, Germany, 1988, pp. 145–159.