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Fachgebiet Datentechnik (DATE)
Prof. Dr. Sybille Hellebrand
Bildinformationen anzeigen

Konferenzbeiträge

  • Logic Fault Diagnosis of Hidden Delay Defects
    2020 S. Holst, M. Kampmann, A. Sprenger, J. D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng
    Proceedings IEEE International Test Conference (ITC'20), Virtual Conference - Ursprünglich Washington, DC, USA, 3-5 November 2020, pp. 1-10
  • Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study
    2020 A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, S. Hellebrand
    Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), Virtual Conference - Ursprünglich Frascati (Rome), Italy, 19-21 October 2020, pp. 1-6
  • Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
    2020 S. Sadeghi-Kohan, S. Hellebrand
    Proceedings IEEE VLSI Test Symposium, pp. 1-6
  • A Hybrid Space Compactor for Adaptive X-Handling
    2019 M. U. Maaz, A. Sprenger, S. Hellebrand
    Proceedings IEEE International Test Conference (ITC'19), Washington, DC, USA, 11-17 November 2019, pp. 1-8
  • Extending Aging Monitors for Early Life and Wear-out Failure Prevention
    2018 C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H. Wunderlich
    Proceedings of the 27th IEEE Asian Test Symposium (ATS'18), Hefei, Anhui, China, 15-18 October 2018, pp. 1-6
  • Tuning Stochastic Space Compaction to Faster-than-At-Speed Test
    2018 A. Sprenger, S. Hellebrand
    Proceedings of 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'18), Budapest, Hungary, April 2018, pp. 73-78
  • Design-for-FAST: Supporting X-tolerant Compaction during Faster-than-at-Speed Test
    2017 M. Kampmann, S. Hellebrand
    Proceedings 20th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'17), Dresden, Germany, April 2017, pp. 39-45
  • Special Session on Early Life Failures
    2017 J. Deshmukh, W. Kunz, H. Wunderlich, S. Hellebrand
    Proceedings of the 35th VLSI Test Symposium (VTS'17), Caesars Palace, Las Vegas, Nevada, USA, 9-12 April 2017
  • X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test
    2016 S. Hellebrand, M. Kampmann
    Proceedings of 25th IEEE Asian Test Symposium (ATS'16), Hiroshima, Japan. November 2016, pp 1-6
  • Optimized Selection of Frequencies for Faster-than-at-Speed Test
    2015 M. Kampmann, M. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H. Wunderlich
    Proceedings Asian Test Symposium (ATS'15), Mumbai, India, November 2015, pp. 109-114
  • FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects
    2014 S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, H. Wunderlich
    Proceedings IEEE International Test Conference (ITC'14), Seattle, Washington USA, October 21-23, 2014
  • Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test
    2012 A. Cook, S. Hellebrand, H. Wunderlich
    Proceedings IEEE European Test Symposium, Annecy, France, May 2012, pp. 1-6
  • Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test
    2012 A. Cook, S. Hellebrand, M. Imhof, A. Mumtaz, H. Wunderlich
    Proceedings Latin American Test Workshop, Quito, Ecuador, April 2012, pp. 1-4
  • Diagnostic Test of Robust Circuits
    2011 A. Cook, S. Hellebrand, T. Indlekofer, H. Wunderlich
    Proceedings 20th Asian Test Symposium, New Delhi, India, November, 2011, pp. 285-290
  • Robuster Selbsttest mit Diagnose
    2011 A. Cook, S. Hellebrand, T. Indlekofer, H. Wunderlich
    5. GMM/GI/ITG Fachtagung "Zuverlässigkeit und Entwurf", Hamburg, September 2011, pp. 48-53
  • Towards Variation-Aware Test Methods
    2011 I. Polian, B. Becker, S. Hellebrand, H. Wunderlich, P. Maxwell
    Proceedings 16th IEEE European Test Symposium, Trondheim, Norway, May 2011 (Embedded Tutorial)
  • Variation-Aware Fault Modeling
    2010 F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich
    Proceedings 19th Asian Test Symposium, Shanghai, China, December 1-4, 2010, pp. 87-93
  • The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems
    2010 M. Hunger, S. Hellebrand
    Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10), Kyoto, Japan, October 2010, pp. 101-108
  • Efficient Test Response Compaction for Robust BIST Using Parity Sequences
    2010 T. Indlekofer, M. Schnittger, S. Hellebrand
    Proceedings 28th IEEE International Conference on Computer Design (ICCD'10), Amsterdam, The Netherlands, October 2010, pp. 480-485
  • Robuster Selbsttest mit extremer Kompaktierung
    2010 T. Indlekofer, M. Schnittger, S. Hellebrand
    4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Wildbad Kreuth, September 2010, pp. 17-24
  • Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz
    2010 M. Hunger, S. Hellebrand
    4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Wildbad Kreuth, September 2010, pp. 81-88
  • Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
    2010 B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich
    4th Workshop on Dependable and Secure Nanocomputing (WDSN'10), Chicago, IL, USA, June 2010 (Invited Paper)
  • Reusing NoC-Infrastructure for Test Data Compression
    2010 V. Fröse, R. Ibers, S. Hellebrand
    Proceedings IEEE VLSI Test Symposium (VTS'10), Santa Cruz, CA, USA, April 2010, pp. 227-231
  • Are Robust Circuits Really Robust?
    2009 S. Hellebrand, M. Hunger
    Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), Chicago, IL, USA, October 2009, p. 77 (Invited Talk)
  • Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung
    2009 M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker
    Proceedings 3. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Stuttgart, September, 2009
  • ATPG-Based Grading of Strong Fault-Secureness
    2009 M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker
    IEEE International On-Line Testing Symposium 2009 (IOLTS'09), Sesimbra-Lisbon, Portugal, June, 2009
  • Modularer Selbsttest und optimierte Reparaturanalyse
    2008 P. Öhler, A. Bosio, G. Di Natale, S. Hellebrand
    Proceedings 2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Ingolstadt, September 2008
  • Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG
    2008 M. Hunger, S. Hellebrand
    Proceedings 2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Ingolstadt, September 2008
  • A Modular Memory BIST for Optimized Memory Repair
    2008 P. Öhler, A. Bosio, G. Di Natale, S. Hellebrand
    IEEE International On-Line Testing Symposium 2008 (IOLTS'08), Rhodos, Greece, July, 2008 (Poster)
  • Verification and Analysis of Self-Checking Properties through ATPG
    2008 M. Hunger, S. Hellebrand
    IEEE International On-Line Testing Symposium 2008 (IOLTS'08), Rhodos, Greece, July, 2008
  • Signature Rollback - A Technique for Testing Robust Circuits
    2008 U. Amgalan, C. Hachmann, S. Hellebrand, H. Wunderlich
    Proceedings IEEE VLSI Test Symposium (VTS’08), San Diego, CA, USA, May, 2008, pp. 125-130
  • Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper)
    2007 S. Hellebrand, C. Zoellin, H. Wunderlich, S. Ludwig, T. Coym, B. Straube
    43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), Bled, Slovenia, September 2007
  • A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
    2007 S. Hellebrand, C. Zoellin, H. Wunderlich, S. Ludwig, T. Coym, B. Straube
    Proceedings 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 2007, pp. 50-58
  • An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
    2007 P. Öhler, S. Hellebrand, H. Wunderlich
    Proceedings 12th IEEE European Test Symposium, Freiburg, Germany, pp.91-96, May 2007
  • A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip
    2007 M. Ali, M. Welzl, S. Hessler, S. Hellebrand
    Proceedings 4th International Conference on Information Technology: New Generations (ITNG'07), Las Vegas, Nevada, USA, April 2007, pp. 1027-1032
  • Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
    2007 P. Öhler, S. Hellebrand, H. Wunderlich
    Proceedings 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Krakow, Poland, pp. 185-190, April 2007
  • Test und Zuverlässigkeit nanoelektronischer Systeme
    2007 B. Becker, I. Polian, S. Hellebrand, B. Straube, H. Wunderlich
    Proceedings 1. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Munich, March 2007
  • Self-checking booth-3 multiplier
    2006 M. Hunger, D. Marienfeld, M. Gössel
    1st. International Conference for Young Researchers in Computer Science, Control, Electrical Engineering and Telecommunications Zielona Góra 2006 (Poster)
  • Considerations for Fault-Tolerant Networks on Chips
    2005 M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand
    Proceedings International Conference on Microelectronics (ICM'05), Islamabad, Pakistan, December 2005
  • A Dynamic Routing Mechanism for Network on Chip
    2005 M. Ali, M. Welzl, S. Hellebrand
    Proceedings 23rd NORCHIP Conference, Oulu Finland, November 2005, pp. 70-73
  • Low Power Embedded DRAMs with High Quality Error Correcting Capabilities
    2005 P. Öhler, S. Hellebrand
    Proceedings 10th IEEE European Test Symposium (ETS'05), Tallinn, Estonia, pp. 148-153, May 2005
  • Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
    2004 A. Wuertenberger, C. Tautermann, S. Hellebrand
    Proceedings IEEE International Test Conference (ITC'04), Charlotte, NC, USA, pp. 926-935, October 2004
  • Sensor Networks with more Features using less Hardware
    2004 M. Liu Jing, S. Rührup, C. Schindelhauer, K. Volbert, M. Dierkes, A. Bellgardt, R. Ibers, U. Hilleringmann
    GOR/NGB Conference Tilburg 2004
  • A Hybrid Coding Strategy for Optimized Test Data Compression
    2003 A. Wuertenberger, C. Tautermann, S. Hellebrand
    Proceedings IEEE International Test Conference (ITC'03), Charlotte, NC, USA, pp. 451-459, September 30 - October 2, 2003
  • Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
    2001 H. Liang, S. Hellebrand, H. Wunderlich
    Proceedings IEEE International Test Conference (ITC'01), Baltimore, MD, USA, pp. 894-902, November 2001
  • A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
    2000 S. Hellebrand, H. Liang, H. Wunderlich
    Proceedings IEEE International Test Conference (ITC'00), Atlantic City, NJ, USA, pp. 778-784, October 2000
  • Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms
    1999 V. Yarmolik, I. Bykov, S. Hellebrand, H. Wunderlich
    Proceedings Third European Dependable Computing Conference (EDCC-3), Prague, Czech Republic, September 15-17, 1999
  • Error Detecting Refreshment for Embedded DRAMs
    1999 S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, V. Yarmolik
    Proceedings 17th IEEE VLSI Test Symposium, Dana Point, CA, USA, pp. 384-390, April 25-29, 1999
  • Symmetric Transparent BIST for RAMs
    1999 S. Hellebrand, H. Wunderlich, V. Yarmolik
    Proceedings Design, Automation and Test in Europe, DATE'99, Munich, Germany, pp. 702-707, March 9-12, 1999
  • New Transparent RAM BIST Based on Self-Adjusting Output Data Compression
    1998 V. Yarmolik, Y. Klimets, S. Hellebrand, H. Wunderlich
    Proceedings Design & Diagnostics of Eletronic Circuits & Systems, Szczyrk, Poland, pp. 27-33, September 1998
  • Fast Self-Recovering Controllers
    1998 A. Hertwig, S. Hellebrand, H. Wunderlich
    Proceedings 16th IEEE VLSI Test Symposium (VTS'98), Monterey, CA, April 1998, pp. 296-302
  • Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
    1998 S. Hellebrand, H. Wunderlich, V. Yarmolik
    Proceedings Design Automation and Test in Europe, DATE'98, Paris, France, February 1998, pp. 173-179
  • STARBIST: Scan Autocorrelated Random Pattern Generation
    1997 K. Tsai, S. Hellebrand, M. Marek-Sadowska, J. Rajski
    Proc. ACM/IEEE Design Automation Conference, Anaheim, CA, June 1997
  • Mixed-Mode BIST Using Embedded Processors
    1996 S. Hellebrand, H. Wunderlich, A. Hertwig
    Proceedings IEEE International Test Conference, Washington, DC, 1996, pp. 195-204
  • Pattern Generation for a Deterministic BIST Scheme
    1995 S. Hellebrand, B. Reeb, S. Tarnick, H. Wunderlich
    Proceedings ACM/IEEE International Conference on Computer-Aided Design (ICCAD'95), San Jose, CA, November 1995, pp. 88-94
  • An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures
    1994 S. Hellebrand, H. Wunderlich
    Proceedings ACM/IEEE International Conference on Computer-Aided Design (ICCAD 94), San Jose, CA, November 1994, pp. 110-116
  • Synthese schneller selbsttestbarer Steuerwerke
    1994 S. Hellebrand, H. Wunderlich
    Tagungsband der GI/GME/ITG-Fachtagung & Rechnergestützer Entwurf und Archtektur mikroelektronischer Systeme, Oberwiesenthal, Mai, 1994 (Informatik Xpress 4, TU Chemnitz Zwickau), pp. 3-11
  • Synthesis of Self-Testable Controllers
    1994 S. Hellebrand, H. Wunderlich
    Proceedings European Design Automation Conference (EDAC/ETC/EuroAsic), Paris, France, March 1994, pp. 580-585
  • An Efficient BIST Scheme Based on Resseding of Multiple Polynomial Linear Feedback Shift Registers
    1993 S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick
    Proceedings ACM/IEEE International Conference on Computer-Aided Design (ICCAD'93)
  • Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
    1992 S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois
    Proceedings IEEE International Test Conference (ITC'92), Baltimore, MD, 1992, pp. 120-129
  • Generating Pseudo-Exhaustive Vectors for External Testing
    1990 S. Hellebrand, H. Wunderlich, O. Haberl
    Proceedings IEEE International Test Conference (ITC'90), Washington, DC, 1990, pp. 670-679
  • Tools and Devices Supporting the Pseudo-Exhaustive Test
    1989 S. Hellebrand, H. Wunderlich
    Proceedings 1st European Design Automation Conference, EDAC, Glasgow, UK, 1990, pp. 13-17
  • The Pseudo-Exhaustive Test of Sequential Circuits
    1989 H. Wunderlich, S. Hellebrand
    Proceedings IEEE International Test Conference (ITC'89), Washington, DC, 1989, pp. 19-27
  • Automatisierung des Entwurfs vollständig testbarer Schaltungen
    1988 S. Hellebrand, H. Wunderlich
    Proceedings GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, Springer-Verlag, pp. 145-159
  • Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits
    1988 H. Wunderlich, S. Hellebrand
    Proceedings 18th International Symposium on Fault-Tolerant Computing, FTCS-18, Tokyo 1988, pp. 36-45
  • Intergrated Tools for Automatic Design for Testability
    1987 D. Schmid, H. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, A. Kunzmann
    In: Tool Integration and Design Environments, F.J. Rammig (Editor), Amsterdam: Elsevier Science Publishers B.V.(North Holland), IFIP, 1988, pp. 233-258

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