The sequential execution of the control algorithm on processor-based controls implies a total dead time TΣ of 1.5*TC (due to the computational delay of one sampling step TC and additional delay of 0.5*TC caused by the data acquisition mechanism). This additional delay has to be considered in the controller design and is typically approximated using a first order lag element with the time delay TΣ. It can be shown that the bandwidth of the closed loop transfer function of the system is inversely proportional to the dead time TΣ. For standard drives the achievable bandwidth of processor-based controls may be sufficient, but for high performance servo drives it is just insufficient. The poor achievable bandwidth directly results in low dynamics. This problem can be overcome by reducing the total dead time of the closed loop transfer function.
Before microcontrollers came up the control realization was based on analog circuits. Such an analog realization does not introduce any dead time in the system, so that the achievable bandwidth is quite high, theoretically even infinite. However the analog realization has its own drawbacks, which are offset, nonlinearity, drift, nonchangeable control parameters, etc. Therefore the goal is to achieve the same performance in the digital domain but avoiding these drawbacks.
A control realization based on FPGA currently seems to be the best approach to achieve a performance that is very close to analog controls on a digital platform. The resulting controls can be referred to as quasi-continuous control realizations. The possibility of parallel execution also enables the handling and implementation of multiple/ complex control schemes on a single control platform. Thus, it is possible to realize a dynamically reconfigurable control structure as shown in Figure 2. The relevant trajectories during transition between a FOC and DTC control structure on a testbench are depicted in Figure 3.