The paper "Variation-Aware Test for Logic Interconnects using Neural Networks – A Case Study" from Alexander Sprenger, Somayeh Sadeghi-Kohan, Jan Dennis Reimer and Sybille Hellebrand was accepted at "33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS'20)".
The conference will take place from October 19th till October 21st 2020.