Alisa Stiballe presents her bachelor thesis on Wednesday, 25.10.2023 at 14:00 in our seminar room P1.6.17.1. The bachelor thesis is titled:
"GPU-based Logic Simulation of Crosstalk related Interconnect Delays".
The presentation will be given in english. Everyone who is interested is welcome to attend the session.
Abstract: The development of computer chips entails a sophisticated process requiring money, advanced knowledge, and time to succeed. Therefore, the validation of computer chips is essential to ensure functionality and to prevent from a utilization of failing hardware. Software-based simulations on gate-level are dominating electrical level simulations in terms of computational needs and execution time, but fall behind in the accuracy of the resulting timing behavior. Especially, the parasitic effects of interconnects, the connections between logic gates, are often fully neglected. However, the recent trend of decreasing technology sizes empowers the influences of parasitic effects, named crosstalk, superseding the gate delays. To cope with missing wire timing behavior, this work introduces a novel approach to model interconnect delays using polynomial regression and machine learning, emphasizing crosstalk between adjacent wires. Embedded in an advanced GPU-accelerated gate-level simulator, the presented interconnect model is able to increase the accuracy and improve the overall simulation performance