Studierender: Rakib Khan Pathan
Betreuer: Jan Dennis Reimer
Abstract: The goal of this master's thesis is to create an efficient and scalable neural network for circuit timing simulation. It aims to overcome the runtime limitations of SPICE simulations while maintaining high accuracy in predicting cell voltages and timing characteristics. The main objective is to develpo a neural network model that is able to perform accurate timing predictions of NAND gates. The model would be trained on SPICE simulation data to predict all voltages within a cell. Moreover, an algorithm will be created to leverage this neural network for efficient circuit timing simulations, overcoming the speed and scalability limitations of traditional SPICE and FastSpice. Finally, we will conduct comprehensive analysis of the neural network model to validate its accuracy and performance at circuit level.