Studierender: Alexander Coers
Betreuerin: Dr. Somayeh Sadeghi-Kohan
Abstract
In today's digital systems, interconnect has an important role and affects the performance, power consumption, and reliability of the circuit. The coupling elements in the interconnects result in glitch and delay faults and therefore functional errors. It is also shown that crosstalk elements increase the current density of wires and therefore, they participate in reliability degradation of the wire and accelerate the wire aging.
Analyzing crosstalk for wires in logic circuits is particularly challenging since all wires in a logic unit need to be considered. This is because all wires between logic gates experience crosstalk and hidden interconnect defects which are normally not considered. One of the strongest tools for modeling and simulating wires and logic elements is HSPICE. However, it suffers from a very slow simulation time because it considered all details of the elements that usually are not required in the first design steps. Therefore, higher-level models are required to accelerate the simulation time for the first design exploration steps.
In this project, our goal is to extract a minimum set of useful information from HSPICE modeling to measure the current and delay of the wire elements, and find the relation between them and extract some formula to be used in the high-level modeling. We need this information because and HSPICE full analysis, including this low-level information in a complex system, requires a lot of effort. To access the effectiveness of our models, they will be tested by utilizing them in a high-level model simulator (C++) and the simulation time and results' precision will be compared with the results of the same system implemented in HSPICE.