Algorithms and Tools for Test and Diagnosis of Systems on Chip

Further information can be found in the corresponding PANDA course.

Description

The course deals with advanced research topics in test and diagnosis of integrated circuits and systems. Major challenges stem from the increasing complexity and heterogeneity of systems, but alsofrom the growing impact of parameter variations in nano-scale technologies. Topics include for example:

Automatic test pattern generation (ATPG): Here the focus of the course lies on efficient heuristics that can handle billions and trillions of gates in complex state of the art systems.
Fault models and tests for interconnections: In particular more realistic failure mechanisms, e.g. for crosstalk faults, as well as built-in test solutions are considered.
Statistical timing analysis: Parameter variations usually manifest themselves as timing deviations. Therefore it is no longer sufficient to work with worst or average case assumptions, but statistical approaches are of growing importance. The course introduces basic techniques for statistical timing modeling and simulation.
On-chip test response compaction: A major problem in response compaction arises from unknown ("X") values during simulation that make test signatures unpredictable. The course therefore deals with recent "X"-tolerating or "X"-masking approaches for test response compaction.