Al­ex­an­der Spren­ger, Somayeh Sade­ghi-Ko­han, and Jan Den­nis Re­imer re­ceived Out­stand­ing Stu­dent Pa­per Award

Alexander Sprenger, Somayeh Sadeghi-Kohan and Jan Dennis Reimer received an Outstanding Student Paper Award for their paper Variation-Aware Test for Logic Interconnects using Neural Networks – A Case Study during the 33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS20)

Modern System-on-Chips are more and more affected by interconnect defects. Crosstalk defects lead to small delay faults and aggravate aging mechanism like electromigration. While interconnects between two systems within the System-on-Chip can be tested directly for interconnect defects, interconnects within the logic are not directly accessible, and defects can be overlapped by parameter variations due to manufacturing inaccuracies. To distinguish between safety-critical interconnect defects and less critical defects, in this work an AI-based solution is presented. It is based on two-dimensional delay maps obtained from testing the microsystem in different operating points. This delay maps can be classified in crosstalk-induced delay maps and variation-induced delay maps using artificial neural networks. With help of this method it is possible to achieve high reliability while maintaining yield during production.