Zeit­schrif­ten

Workload-Aware Periodic Interconnect BIST

S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &Test (2023) 1–1.

DOI
Stress-Aware Periodic Test of Interconnects

S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing (2022).

DOI
Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test

A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers 28 (2019) 1–23.

DOI
Built-in Test for Hidden Delay Faults

M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38 (2019) 1956–1968.

Guest Editors' Introduction - Special Issue on Approximate Computing

S. Hellebrand, J. Henkel, A. Raghunathan, H.-J. Wunderlich, IEEE Embedded Systems Letters 10 (2018) 1–1.

DOI
Design For Small Delay Test - A Simulation Study

M. Kampmann, S. Hellebrand, Microelectronics Reliability 80 (2018) 124–133.

Self-Adjusting Monitor for Measuring Aging Rate and Advancement

S. Sadeghi-Kohan, M. Kamal, Z. Navabi, IEEE Transactions on Emerging Topics in Computing 8 (2017) 627–641.

DOI
A High Performance SEU Tolerant Latch

Z. Huang, H. Liang, S. Hellebrand, Journal of Electronic Testing - Theory and Applications (JETTA) 31 (2015) 349–359.

SAT-Based ATPG beyond Stuck-at Fault Testing

S. Hellebrand, H.-J. Wunderlich, DeGruyter Journal on Information Technology (It) 56 (2014) 165–172.

Adaptive Bayesian Diagnosis of Intermittent Faults

L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 30 (2014) 527–540.

A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs

B. Alizadeh, P. Behnam, S. Sadeghi-Kohan, IEEE Transactions on Computers (2014) 1–1.

DOI
Variation-Aware Fault Modeling

F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer 54 (2011) 1813–1826.

Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance

S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, Informacije MIDEM, Ljubljana (Invited Paper) 37 (2007) 212–219.

An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip

M. Ali, S. Hessler, M. Welzl, S. Hellebrand, International Journal on High Performance Systems Architecture 1 (2007) 113–123.

DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme

B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, It - Information Technology 48 (2006) 305–311.

Efficient Online and Offline Testing of Embedded DRAMs

S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, IEEE Transactions on Computers 51 (2002) 801–809.

DOI
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST

S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 18 (2002) 157–168.

A Mixed-Mode BIST Scheme Based on Folding Compression

H. Liang, S. Hellebrand, H.-J. Wunderlich, Journal on Computer Science and Technology 17 (2002) 203–212.

Deterministic BIST Scheme Based on Reseeding of Folding Counters

H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, Journal of Computer Research and Development, (Jisuanji Yanjiu Yu Fazhan) 38 (2001) 931.

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters

S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 17 (2001) 341–349.

Mixed-Mode BIST Using Embedded Processors

S. Hellebrand, H.-J. Wunderlich, A. Hertwig, Journal of Electronic Testing Theory and Applications - JETTA 12 (1998) 127–138.

Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications

S. Hellebrand, A. Hertwig, H.-J. Wunderlich, IEEE Design and Test 15 (1998) 36–41.

Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, IEEE Transactions on Computers 44 (1995) 223–233.

DOI
The Pseudoexhaustive Test of Sequential Circuits

H.-J. Wunderlich, S. Hellebrand, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 11 (1992) 26–33.

DOI
Alle Publikationen anzeigen
Sie interessieren sich für: