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Bebot-Roboter aus dem Fachgebiet Schaltungstechnik am Institut für Elektrotechnik, Foto: Universität Paderborn, Fotografin: Judith Kraft Bildinformationen anzeigen

Bebot-Roboter aus dem Fachgebiet Schaltungstechnik am Institut für Elektrotechnik, Foto: Universität Paderborn, Fotografin: Judith Kraft

apl. Prof. Dr. Wolfgang Müller

Kontakt
Publikationen
apl. Prof. Dr. Wolfgang Müller

Schaltungstechnik (SCT) / Heinz Nixdorf Institut

Apl. Professor

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+49 5251 60-6352
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33102 Paderborn

Liste im Research Information System öffnen

2021

Register and Instruction Coverage Analysis for Different RISC-V ISA Modules

P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2021), 2021


2020

A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures

P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, 2020

Fault effect simulation is a well-established technique for the qualification of robust embedded software and hardware as required by different safety standards. Our article introduces a Virtual Prototype based approach for the fault analysis and fast simulation of a set of automatically generated and target compiled software programs. The approach scales to different RISC-V ISA standard subset configurations and is based on an instruction and hardware register coverage for automatic fault injections of permanent and transient bitflips. The analysis of each software binary evaluates its opcode type and register access coverage including the addressed memory space. Based on this information dedicated sets of fault injected hardware models, i.e., mutants, are generated. The simulation of all mutants conducted with the different binaries finally identifies the cases with a normal termination though executed on a faulty hardware model. They are identified as a subject for further investigations and improvements by the implementation of additional hardware or software safety countermeasures. Our final evaluation results with automatic C code generation, compilation, analysis, and simulation show that QEMU provides an adequate efficient platform, which also scales to more complex scenarios.


2019

RISC-V Extensions for Bit Manipulation Instructions

B. Koppelmann, P. Adelt, W. Müller, C. Scheytt, in: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2019

Embedded systems require a high energy efficiency in combination with an optimized performance. As such, Bit Manipulation Instructions (BMIs) were introduced for x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled software for various applications. Though the RISC-V platform is meanwhile widely accepted for embedded systems application, its instruction set architecture (ISA) currently still supports only two basic BMIs.We introduce ten advanced BMIs for the RISC-V ISA and implemented them on Berkeley's Rocket CPU [1], which we synthesized for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket CPU hardware extensions show that RISC-V BMI extensions have no negative impact on the critical path of the execution pipeline. Our software evaluations show that we can, for example, expect a significant impact for time and power consuming cryptographic applications.


Analyse sicherheitskritischer Software für RISC-V Prozessoren

P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2019), 2019

In diesem Artikel stellen wir eine Methode zur nicht-invasiven dynamischen Speicher- und IO-Analyse mit QEMU für sicherheitskritische eingebettete Software für die RISC-V Befehlssatzarchitektur vor. Die Implementierung basiert auf einer Erweiterung des Tiny Code Generator (TCG) des quelloffenen CPU-Emulators QEMU um die dynamische Identifikation von Zugriffen auf Datenspeicher sowie auf an die CPU angeschlossene IO-Geräte. Wir demonstrieren die Funktionalität der Methode anhand eines Versuchsaufbaus, bei dem eine Schließsystemkontrolle mittels serieller UART-Schnittstelle an einen RISC-V-Prozessor angebunden ist. Dieses Szenario zeigt, dass ein unberechtigter Zugriff auf die UART-Schnittstelle frühzeitig aufgedeckt und ein Angriff auf eine Zugangskontrolle somit endeckt werden kann.


QEMU for Dynamic Memory Analysis of Security Sensitive Software

P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, B. Driessen, in: 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019, 2019, pp. 32-34


QEMU Support for RISC-V: Current State and Future Releases

P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, 2nd International Workshop on RISC-V Research Activities (2019), (Presentation)

It its current Version 3.1.0 QEMU supports RISC-V RV32GC and RV64GC software emulation in user and full system mode. We will first give an overview of the current state of the QEMU RISC-V implementation. Thereafter, we will present the DecodeTree tool, which will be available with the next QEMU release. DecodeTree is a code generator included in QEMU that can generate the program logic for extracting and decoding opcodes and operands from a formal instruction list of the target architecture. This enables the structured implementation of just-in-time compilations to guarantee that the QEMU implementation meets the ISA specification. As such, we completely replaced the existing RISC-V RV32GC and RV64GC implementations by DecodeTree generations in the next official QEMU release, which is expected in spring 2019. We will demonstrate the DecodeTree applications by the example of RISC-V ISA subset configurations.


2018

Current and Future RISC-V Activities for Virtual Prototyping and Chip Design

P. Adelt, B. Koppelmann, W. Müller, International Workshop on RISC-V Research Activities (2018), Presentation


Analog fault simulation automation at schematic level with random sampling techniques

L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, 2018

This paper presents an approach for analog fault effect simulation automation based on random fault selection with a high fault coverage of the circuit under test by means of fault injection and simulation based on advanced sampling techniques. The random fault selection utilizes the likelihood of the fault occurrence of different electrical components in the circuit with a confidence level. Defect models of different devices are analyzed for the calculation of the fault probability. A case study with our implemented tool demonstrates that likelihood calculation and fault simulation provides means for efficient fault effect simulation automation.


2017

ANALISA - A Tool for Static Instruction Set Analysis

P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation, 2017


ANALISA - A Tool for Static Instruction Set Analysis

P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, J.C. Scheytt, in: Design Automation and Testing in Europe (DATE), 2017


An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries

P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 2017, pp. 44


Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen

P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, C. Scheytt, in: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017


SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study

L. Wu, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), 2017, pp. 68

This paper presents the design flow of using sampling technique for fault injection on sche- matic level. The parameters used in the docu- ment to calculate the likelihood could be modi- fied by using more realistic data from the fab. With the help of the fault simulator, the whole design flow of the fault effect simulation can be realized automatically.


2016

Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study

S. Abughannam, L. Wu, W. Müller, C. Scheytt, in: Analog 2016 - VDE, 2016

The design of safety critical systems requires an efficient methodology for an effective fault effect simulation for analog and digital circuits where analog fault injection and fault effect simulation is currently a field of active research and commercial tools are not available yet. This article begins by discussing fault injection strategies for analog circuits applied on a case study with two topologies of a Voltage Controlled Oscillator (VCO). In the second part it performs on the basis of the example of a Wireless Sensor Network (WSN) node, how far different mixed level implementations with Verilog-A and SPICE can affect the simulation time and points out which component consumes the major part of the simulation time.


Fast Dynamic Fault Injection for Virtual Microcontroller Platforms

P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, C. Scheytt, in: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC), 2016

Electronic systems, like they are embedded in road vehicles, have to be compliant to functional safety standards like ISO 26262 [1], which limit the impacts of malfunctions for safety critical systems. ISO 26262, for instance, defines different safety levels for road vehicles, which require different means and measures for a safety compliant system and its development process like risk analysis and fault effect simulation. For fault effect simulation it is important to investigate the impact of physical and hardware related effects to the correct function of a system. This article first studies code and model mutations for fault injection in the context of fault effect simulation through different system abstraction levels. It demonstrates how high level mutations correlate to bit flips of software binaries by examples from the TriCore™ instruction set and finally presents a virtual platform based implementation for automated injection of bit flip based mutations into software binaries. Experimental results demonstrate the efficiency of the implemented approach.


2015

On the Correlation of HW Faults and SW Errors

W. Müller, L. Wu, C. Scheytt, M. Becker, S. Schoenberg, in: Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), 2015


2014

Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software

M. Becker, C. Kuznik, W. Müller, in: 17th Euromicro Conference on Digital Systems Design (DSD), 2014


HeroeS³ -- A Framework for Heterogeneous Software-Intensive System Design with SystemC

M. Becker, W. Müller, J. Stroop, U. Kiffmeier, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014)


Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges

J. Oetjens, M. Becker, C. Kuznik, W. Müller, in: Design Automation Conference (DAC), 2014


Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU

B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, C. Scheytt, Design and Verification Conference (DVCON EUROPE) (2014)


Source code annotated memory leak detection for soft real time embedded systems with resource constraints

M.t.M.M. Joy, W. Müller, F. Rammig, in: 12th IEEE International conference on Embedded Computing, 2014


Portierung der TriCore-Architektur auf QEMU

B. Koppelmann, M. Becker, W. Müller, in: 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) , 2014


Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM

C. Kuznik, W. Müller, in: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2014

Zur Sicherstellung hoher Zuverlässigkeits- und Fehlertoleranzwerte von Schaltungen und ganzen Systemen finden vermehrt Test- und Verifikationsmethoden Anwendung die einen virtuellen Prototypen (VP) des Systems bereits frühzeitig im Entwurfsablauf einem Stresstest unterziehen. Hierbei werden speziell für die Domäne relevante Fehlerinjektoren verwendet (Digital, Mixed-Signal, Mechanik) die anhand von Fehlermodellen geeignete Testfälle erzeugen und in das System über Stimuli bzw. direkt injizieren. Jede effektive Anwendung einer Methode bedingt jedoch auch das Vorhandensein einer zugrundeliegenden Methodik. In diesem Beitrag wird die System Verification Methodology (SVM) vorgestellt werden, eine universell einsetzbare und erweiterbare Infrastruktur zur Beschreibung von Testumgebungen auf Basis der SystemC Sprache und Simulationskernels.


Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure

C. Kuznik, W. Müller, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014)

Verific-MM is an approach to systematize and accelerate the coverage plan engineering as well as the verification environment’s (functional) metric code generation -- usually a time-consuming and error-prone task -- in particular by (i) improving automation via assisted model-based approaches, utilizing recent industry standards such as UCIS and (ii) a supporting methodology suitable for various target (functional coverage) languages (IEEE-1800 SystemVerilog, IEEE-1647 e, IEEE-1666 SystemC).


Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges

J. Oetjens, M. Becker, C. Kuznik, W. Müller, in: Design Automation Conference (DAC), 2014

Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults. Additionally, Virtual Prototypes (VPs) have been accepted in many areas of system development processes in the automotive industry as platforms for SW development, verification, and design space exploration. We believe that VPs will significantly contribute to the analysis of safety conditions for automotive electronics. This paper shows the advantages of such a methodology based on today's industrial needs, presents the current state of the art in this field, and outlines upcoming research challenges that need to be addressed to make this vision a reality.


Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU

B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, J.C. Scheytt, Design and Verification Conference (DVCON EUROPE) (2014)


Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems

M. Becker, C. Kuznik, W. Müller, in: ACM/IEEE 5th International Conference on Cyber-Physical Systems, 2014


Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure

C. Kuznik, W. Müller, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014)


Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation

F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, 2014

Energy efficiency drives the development of more and more complex low-power designs. Based on dynamic power management techniques, multiple voltage islands as well as a huge amount of power states are specified that have to be tested carefully. In this context, low-power design should start at an early stage using state-of-the-art system-level modeling and simulation techniques. However, there is neither a programming language nor any modeling standard that reflects variable power together with its functional side effects in a well-suited abstract manner. To overcome this limitation, we present a modeling approach on top of SystemC TLM to capture low-power design characteristics at electronic system-level. We demonstrate the usability by means of an existing open-source low-power design. The experimental results show that appropriate TLM instrumentation cause only minimal simulation overhead, but offer sufficient details to identify common low-power design errors.


Architectural Low-Power Design Using Transaction-Based System Simulation

F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, 2014



An Assisted Single Source Verification Metric Model Code Generation Methodology

C. Kuznik, B.G. Defo, W. Müller, Electronic System Level Synthesis Conference (ESLSyn) (2014)


Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung

C. Kuznik, B.G. Defo, W. Müller, in: 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) , 2014


2013

Efficient Power Intent Validation Using Loosely-Timed Simulation Models

F. Mischkalla, W. Müller, in: 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013, 2013


HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures

M. Becker, U. Kiffmeier, W. Müller, in: 16th IEEE Computer Society Symposium on Object/Component/Service-oriented Real-time Distributed Computing, 2013


SC OVM: An Advanced SystemC Library for OVM-based Verification

C. Kuznik, M. F. S. Oliveira, W. Müller, in: Open SANITAS SystemC Verification Workshop, 2013


Informationstechnik spart Ressourcen

G. Engels, C. Gerth, L. Kleinjohann, B. Kleinjohann, W. Müller. Informationstechnik spart Ressourcen. 2013.


Methods for the Design and Development

H. Anacker, M. Dellnitz, K. Flaßkamp, S. Grösbrink, P. Hartmann, C. Heinzemann, C. Horenkamp, L. Kleinjohann, B. Kleinjohann, S. Korf, M. Krüger, W. Müller, S. Ober-Blöbaum, S. Oberthür, M. Porrmann, C. Priesterjahn, W. Radkowski, C. Rasche, J. Rieke, M. Ringkamp, K. Stahl, D. Steenken, J. Stöcklein, R. Timmermann, A. Trächtler, K. Witting, T. Xie, S. Ziegert, in: Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future, Springer-Verlag, 2013, pp. 187-356


Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model

M.t.M.M. Joy, W. Müller, F. Rammig, in: Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,, Linköping University Electronic Press, 2013


Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen

F. Mischkalla, W. Müller, in: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013


AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS

D. He, W. Müller, in: Proceedings of International Conference on Applied Computing (AC), 2013


SystemC Verification Components - An enhanced OVM/UVM for SystemC

C. Kuznik, M. F. S. Oliveira, W. Müller, in: edaWorkshop 13, 2013


Systematic Application of UCIS to Improve the Automation on Verification Closure

C. Kuznik, M.F. Oliveira, B. Defo, W. Müller, in: Proceedings of DVCON, 2013


Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks

K. Klobedanz, J. Jatzkowski, A. Rettberg, W. Müller, in: International Embedded Systems Symposium (IESS) 2013, Springer, 2013


A heuristic energy-aware approach for hard real-time systems on multi-core platforms

D. He, W. Müller, Microprocessors and Microsystems - Embedded Hardware Design 37(6-7) (2013), pp. 845-857


2012

XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software

M. Becker, D. Baldin, C. Kuznik, M.t.M.M. Joy, T. Xie, W. Müller, in: EMSOFT'12: Teenth ACM International Conference on Embedded Software 2012 Proceedings , 2012


Enhanced Schedulability Analysis of Hard Real-Time Systems on Power Manageable Multi-Core Platforms

D. He, W. Müller, in: Third International Symposium on Advances in Embedded Systems and Applications (ESA-2012), IEEE Xplore, 2012


XEMU: A QEMU Based Binary Mutation Testing Framework

M. Becker, C. Kuznik, M.t.M. Joy, T. Xie, W. Müller, in: Design, Automation and Test in Europe DATE, 2012


Virtual Prototyping of Cyber-Physical Systems

W. Müller, M. Becker, H. Zabel, A. Elfeky, A. DiPasquale, in: In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012, 2012


The System Verification Methodology for Advanced TLM Verification

M.F. Oliveira, C. Kuznik, H.M. Le, D. Große, F. Haedicke, W. Müller, R. Drechsler, W. Ecker, V. Esen, in: CODES/ISSS '12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings, 2012


Compilation of Methodologies to Speed up the Verification Process at System Level

S. Radke, S. Rülke, M.F. Oliveira, C. Kuznik, W. Müller, W. Ecker, V. Esen, S. Hufnagel, N. Bannow, J. Oetjens, H. Brazdrum, P. Janssen, H.M. Le, D. Große, F. Haedicke, R. Drechsler, G. Koch, A. Burger, O. Bringmann, W. Rosenstiel, R. Görgen, in: edaWorkshop 12, 2012


Online Energy-Efficient Hard Real-Time Scheduling for Component Oriented Systems

D. He, W. Müller, in: 2012 IEEE 15th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC), IEEE Xplore, 2012


A SystemC Library for Advanced TLM Verification

M.F. Oliveira, C. Kuznik, W. Müller, W. Ecker, V. Esen, in: Proceeding of Design and Verification Conference (DVCON), 2012


MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution

M. Becker, G.B. Gnokam Defo, W. Müller, F. Fummi, G. Pravadelli, S. Vinco, in: Design, Automation and Test in Europe (DATE 2012), 2012


A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms

D. He, W. Müller, in: 15th Euromicro Conference on Digital System Design (DSD), IEEE Xplore, 2012


Automated Source Code Annotation for Timing Analysis of Embedded Software

M.t.M.M. Joy, M. Becker, E. Mathews, W. Müller, in: In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012), IEEE, 2012


SYSTEMC UVM VERIFICATION COMPONENTS

C. Kuznik, M.F. Oliveira, W. Müller, Design, Automation and Test in Europe DATE (2012)

We present an enhanced UVM for SystemC library which incorporates verification best practices from OVM-ML and UVM as well as project partner implementations. Moreover, we extended functionality and implemented missing features, such as domain specific components, stimuli sequence generation and management, call-back facilities, response to request routing, transaction recording and many more. Apart from that, we added crucial verification components, such as functional coverage.


Binary Mutation Testing Through Dynamic Translation

M. Becker, C. Kuznik, M.t.M.M. Joy, T. Xie, W. Müller, in: 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2012


2011

Aspect enhanced functional coverage driven verification in the SystemC HDVL

C. Kuznik, W. Müller, in: Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011), 2011


HDL-Mutation Based Simulation Data Generation by Propagation Guided Search

T. Xie, W. Müller, in: Proceedings of the 14th Euromicro Conference on Digital System Design (DSD), 2011


A Reconfiguration Approach for Fault-Tolerant FlexRay Networks

K. Klobedanz, A. König, W. Müller, in: Proceedings of Design, Automation, Test Europe - DATE2011, IEEE Computer Society Press, 2011


Self-Reconfiguration for Fault-Tolerant FlexRay Networks

K. Klobedanz, A. König, W. Müller, A. Rettberg, in: Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011, IEEE Computer Society Press, 2011


IP-XACT based System Level Mutation Testing

T. Xie, W. Müller, in: Proceedings of the 16th IEEE International High Level Design Validation and Test Workshop (HLDVT), 2011


Extending UML for Electronic Systems Design: A Code Generation Perspective

Y. Vanderperren, W. Müller, D. He, F. Mischkalla, W. Dahaene, in: Design Technology for Heterogeneous Embedded Systems,1st ed., Springer Verlag, 2011

The Unified Modeling Language (UML) is now widely accepted by the software community. More recently, UML has attracted attention as a unification language for systems description combining both hardware and software components. First, it has been recognized that electronic systems design can no longer be seen as an isolated hardware design activity. In addition, recent advances in tools supporting high level hardware synthesis from electronic system level languages, which are predominantly based on C/C++, open new perspectives for automatic code generation from UML models and opportunities to enhance the link between a high level specification and a concrete hardware/software implementation. Finally, UML has become a general purpose language which can be customized for specific purposes, such as the modelization of electronic systems. This chapter presents recent advances of the UML language applied to System-on-Chip (SoC) and hardware-related embedded systems design. In particular, several examples of specific UML customizations (UML profiles) relevant for SoC design are summarized. Various approaches associating UML with existing hardware/software design languages are presented. The question of tool support and association with well-known simulation environments, such as MATLAB/Simulink, is addressed as well. A concrete example of a UML profile for hardware/software co-modeling and code generation for hardware/software co-simulation is presented in more details for illustration purposes.


Virtual Prototyping softwareintensiver mechatronischer Systeme – Eine Fallstudie

M. Becker, H. Zabel, W. Müller, A. Elfeky, A. DiPasquale, in: 8. Paderborner Workshop Entwurf mechatronischer Systeme, Band 294, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2011, pp. 315-327


Functional Coverage-driven Verification with SystemC on Multiple Level of Abstraction

C. Kuznik, W. Müller, in: Proceedings of DVCON , 2011

SystemC is a versatile C++ based design and verification language, offering various mechanisms and constructs required for embedded systems modeling. Using the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli techniques may be used for verification. However, SCV has several drawbacks such as lack of a functional coverage facility supporting coverage collection on RTL and TLM models. In this article we present a functional coverage library which implements parts of the IEEE 1800-2005 SystemVerilog standard capturing functional coverage throughout the design and verification process, and allows to facilitate coverage-driven verification in SystemC.


Synchronisation eines SystemC Restbus-Simulators mit einem Hardware-In-the-Loop FlexRay Netzwerk

G.B. Gnokam Defo, W. Müller, in: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011


Native binary mutation analysis for embedded software and virtual prototypes in SystemC

C. Kuznik, W. Müller, in: Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing, 2011

Mutation analysis is a powerful tool for white-box testing of the verification environment in order to produce dependable and higher quality software products. However, due to high computational costs and the focus on high-level software languages such as Java mutation analysis is not yet widely used in commercial design flows targeting embedded (software) systems. Here the industry is modeling both hardware and related software parts at higher levels of abstraction, called virtual prototypes, to accelerate parallel development and shorten time-to-market. In this paper we propose a mutation testing verification flow for SystemC based virtual prototypes that may not rely on source code only but on annotated basic blocks and enables mutant creation at assembler level to heavily reduce execution costs and equivalence mutants likelihood.


A Retargetable SysML-based Front-End for High-Level Synthesis

F. Mischkalla, D. He, W. Müller, in: Proceedings of 2nd Workshop on Model Based Engineering for Embedded Systems Design (M-BED), 2011

UML profiles like SysML and MARTE have been a major research topic in electronic system design, but are mainly applied for specification and analysis in early design phases. High-Level Synthesis (HLS), however, addresses the physical implementation aspect of electronic systems, and thus leads to different requirements on the accuracy of models. For this, modular interfaces are a novel object-oriented synthesizable technique to overcome the conflict between a higher degree of abstraction and necessary details for further synthesis. In this paper, we present our approach to use SysML as an adequate modeling language for modular interfaces and C/C++/SystemC-based HLS. We extended SysML with annotations for synthesizable SystemC and high-level synthesis constraints and implemented a code generation scheme to achieve design flow automation. Based on the SysML editor Artisan Studio and an industrial case study, we demonstrate the applicability of SysML as a retargetable front-end for HLS design flows.


Verification Closure of SystemC Designs with Functional Coverage

C. Kuznik, W. Müller, North American SystemC User Group Meeting (16th) (2011)

In the area of dynamic verification of virtual prototypes, functional coverage is a valuable tool for answering the "Are we done?" question and achieving verification closure. Recent verification methodologies such as OVM and UVM contain multi-language support that provides a basic SystemC version. However, due to language shortcoming they cannot be utilized for the same amount of verification tasks in the SystemC ecosystem as in other supported hardware design and verification languages. In this presentation, we propose to boost the verification capabilities of SystemC by implementing functional coverage collection and evaluation according to the same metric as defined in the widely accepted IEEE-1800 SystemVerilog cover group feature. We implement a functional coverage library to enable coverage-driven verification of SystemC designs on multiple levels of abstraction enabling value, transition, and expression coverage. To our knowledge, the overall functionalities are not available in the IEEE-1666 SystemC standard or the SCV add-on library, nor are they complete compared to the aforementioned in any publicly available SystemC library.


A SysML-based Framework with QEMU-SystemC Code Generation

D. He, F. Mischkalla, W. Müller, in: Proceedings of 1st international QEMU Users Forum, 2011


1998

Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen

W. Müller, F. Rammig, Heinz Nixdorf Institut, Universität Paderborn, 1998


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