apl. Prof. Dr. Wolfgang Müller

Kontakt
Publikationen
apl. Prof. Dr. Wolfgang Müller

Schaltungstechnik (SCT) / Heinz Nixdorf Institut

Apl. Professor

Telefon:
+49 5251 60-6352
Büro:
F0.431
Web:
Besucher:
Fürstenallee 11
33102 Paderborn

Publikationen

Aktuelle Publikationen

Scale4Edge – Scaling RISC-V for Edge Applications
W. Ecker, M. Krstic, M. Ulbricht, A. Mauderer, E. Jentzsch, A. Koch, B. Koppelmann, W. Müller, B. Sadiye, N. Bruns, R. Drechsler, D. Müller-Gritschneder, J. Schlamelcher, K. Grüttner, J. Bormann, W. Kunz, R. Heckmann, G. Angst, R. Wimmer, B. Becker, T. Faller, P. Palomero Bernardo, O. Brinkmann, J. Partzsch, C. Mayr, in: Scale4Edge – Scaling RISC-V for Edge Applications, 2023.
A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology
M. Iftekhar, H. Nagaraju, P. Kneuper, B. Sadiye, W. Müller, J.C. Scheytt, in: BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023.
The Scale4Edge RISC-V Ecosystem
W. Ecker, P. Adelt, W. Müller, R. Heckmann, M. Krstic, V. Herdt, R. Drechsler, G. Angst, R. Wimmer, A. Mauderer, R. Stahl, K. Emrich, D. Mueller-Gritschneder, B. Becker, P. Scholl, E. Jentzsch, J. Schlamelcher, K. Grüttner, P.P. Bernardo, O. Brinkmann, M. Damian, J. Oppermann, A. Koch, J. Bormann, J. Partzsch, C. Mayr, W. Kunz, in: In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.
Register and Instruction Coverage Analysis for Different RISC-V ISA Modules
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.
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